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Details, datasheet, quote on part number:ICS9248SB-131
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| Part: | ICS9248SB-131 |
| Category: | Timing Circuits => Clock Generators => CPU/Memory Specific PLL |
| Description: | Frequency Generator & Integrated Buffers For Celeron & Pii/iii(tm) |
| Company: | Integrated Circuit System |
| Datasheet: | Download ICS9248SB-131 datasheet File size : 511 kB |
| Request For quote: | Find where to buy ICS9248SB-131
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9248-131
Frequency Generator & Integrated Buffers for Celeron & PII/IIITM
Recommended Application: ALI - Aladdin V - mobile style chipsets Output Features: 3 - CPUs @ 2.5/3.3V, up to 100MHz. 3 - AGPCLK @ 3.3V 13 - SDRAM @ 3.3V 6 - PCI @ 3.3V 1 - 48MHz, @ 3.3V fixed. 1 - REF @ 3.3V, 14.318MHz. Features: Support power management: CPU, PCI, AGP stop and Power down Mode from I2C programming. Spread spectrum for EMI control. Uses external 14.318MHz crystal FS pins for frequency select Key Specifications: CPU CPU: <250ps AGP PCI: <550ps CPU(early)-PCI: 1-4ns, Center 2-6ns
Pin Configuration
VDDF *REF0/CPU2.5_3.3# GND X1 X2 VDDPCI *PCICLK_F/FS1 *PCICLK0/FS2 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDA BUFFERIN GND *CPU_STOP#/SDRAM11 *PCI_STOP#/SDRAM10 VDDSDR *AGP_STOP#/SDRAM9 *PD#/SDRAM8 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDAGP AGP0 AGP1 GND CPUCLK0 CPUCLK1 VDDL CPUCLK2 SDRAM12 GND SDRAM0 SDRAM1 VDDSDR SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 GND 48MHz/FS0* AGP_F/MODE*
48-Pin SSOP
Block Diagram
PLL2 48MHz
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Functionality
FS 2 FS 1 1 1 0 0 1 1 0 0 FS 0 1 0 1 0 1 0 1 0 C PU , SDRA M (MHz) 1 00 9 5 .2 5 8 3 .3 97 9 1 .5 9 6 .2 2 6 6 .6 7 60 PC I (MHz) 3 3 .3 3 3 1 .7 5 3 3 .3 0 3 2 .3 3 3 0 .5 0 3 2 .0 7 3 3 .3 3 3 0 .0 0 A GP (MHz) 6 6 .6 7 6 3 .5 0 6 6 .6 0 6 4 .6 6 6 1 .0 0 6 4 .1 5 6 6 .6 7 6 0 .0 0 1 1 1 1 0 0 0 0
X1 X2
XTAL OSC PLL1 Spread Spectrum
REF
CPU DIVDER
Stop
3
CPUCLK (2:0)
CPU2.5_3.3# SDATA SCLK FS (2:0) PD# PCI_STOP# CPU_STOP# SDRAM_STOP# AGP-STOP# MODE BUFFERIN Control Logic
PCI DIVDER
Stop
5
PCICLK (4:0) PCICLK_F
AGP DIVDER
Stop
2
AGP (1:0) AGP_F
Note: REF & IOAPIC = 14.318MHz
Config. Reg.
Power Groups
Analog
13
Digital VDDPCI VDDSDR VDDAGP
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
SDRAM (12:0)
VDDF VDDA
9248-131 Rev B 7/17/00
I C S reserves the right to make changes in the device data identified in t h i s publication without further notice. ICS advises its customers to o b t a i n the latest version of all device data to verify that any i n f o r m a t i o n being relied upon by the customer is current and accurate.
ICS9248-131
ICS9248-131
Pin Descriptions
PIN NUMBER 1, 6, 14, 19, 30, 36, 48 2 C P U 2 . 5 _ 3 . 3 # 1,2 3,9,16,22,27, 33,39,45 4 5 GND X1 X2 PCICLK_F 7 FS11, 2 8 13, 12, 11, 10 15 17 PCICLK0 FS21, 2 PCICLK(4:1) BUFFERIN CPU_STOP#1 SDRAM 11 18 40, 28, 29, 31, 32, 34, 35, 37, 38 20 PCI_STOP# SDRAM 10 SDRAM (12, 7:0) AGP_STOP# SDRAM9 21 23 24 25 PD# SDRAM8 SDATA SCLK AGP_F MODE1, 2 48MHz 26 41, 43, 44 42 46, 47 FS01, 2 CPUCLK(2:0) VDDL AGP (1:0)
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P I N NA M E VDD REF0
TYPE PWR OUT IN PWR IN OUT OUT IN OUT IN OUT IN IN OUT IN OUT OUT IN OUT IN OUT I/O IN OUT IN OUT IN OUT PWR OUT Power supply, nominal 3.3V 14.318 Mhz reference clock.
DESCRIPTION
Indicates whether VDDL is 3.3V or 2.5V. High=2.5V CPU, LOW=3.3V C P U 1. L a t c h e d i n p u t 2 Ground Crystal input, has internal load cap (33pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (33pF) Free running PCI clock output. Synchronous with CPUCLKs with 1-4ns skew (CPU early) This is not affected by PCI_STOP# Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Frequency select pin. Latched Input PCI clock outputs. Synchrounous CPUCLKs with 1-4ns skew (CPU early) Input pin for SDRAM buffers. Halts CPUCLK clocks at logic 0 level, when input low (in Mobile Mode, MODE=0) SDRAM clock output Halts PCICLK clocks at logic 0 level, when input low (In mobile mode, MODE=0) SDRAM clock output SDRAM clock outputs. This asynchronous input halts AGP clocks at logic "0" level when input low (in Mobile Mode, MODE=0) Does not affect AGP0 SDRAM clock output This asyncheronous Power Down input Stops the VCO, crystal & internal clocks when active, Low. (In Mobile Mode, MODE=0) SDRAM clock output Data pin for I2C circuitry 5V tolerant Clock pin of I2C circuitry 5V tolerant Advanced Graphic Port output, Not affected by AGP_STOP# Pin 17, 18, 20 & 21 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. 48MHz output clock for USB timing. Frequency select pin. Latched Input. Along with other FS pins determins the CPU, SDRAM, PCI & AGP frewuencies. CPU clock outputs, powered by VDDL. Low if CPU_STOP#=Low Supply for CPU, either 2.5V or 3.3V nominal Advanced Graphic Port outputs
Notes: 1: Internal Pull-up Resistor of 240K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9248-131
General Description
The ICS9248-131 generates all clocks required for high speed RISC or CISC microprocessor systems such as Intel PentiumPro or Cyrix. Eight different reference frequency multiplying factors are externally selectable with smooth frequency transitions. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-131 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations. Serial programming I2C interface allows changing functions, stop clock programming and frequency selection. The SDRAM12 output may be used as a feed back into an off chip PLL.
Mode Pin - Power Management Input Control
MODE, Pin 25 (Latched Input) 0 1 Pin 17 CPU_STOP# (INPUT) SDRAM 11 (OUTPUT) Pin 18 PCI_STOP# (INPUT) SDRAM 10 (OUTPUT) Pin 20 AGP_STOP# (INPUT) SDRAM 9 (OUTPUT) Pin 21 PD# (INPUT) SDRAM 8 (OUTPUT)
Power Management Functionality
AGP_STOP# CPU_STOP# PCI_STOP# 1 1 1 0 0 1 1 1 1 1 0 1 AGP, CPUCLK Outputs Stopped Low Running Running Running PCICLK (4:0) Running Running Stopped Low Running PCICLK_F, REF, 48MHz and SDRAM Running Running Running Running Crystal OSC Running Running Running Running VCO Running Running Running Running AGP (1:0) Running Running Running Stopped Low
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
CPU3.3#_2.5 Input level (Latched Data) 1 0 Buffer Selected for operation at: 2.5V VDD 3.3V VDD
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