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Details, datasheet, quote on part number:ICS9248SB-143
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| Part: | ICS9248SB-143 |
| Category: | Timing Circuits => Clock Generators => CPU/Memory Specific PLL |
| Description: | Frequency Generator & Integrated Buffers For Pentium Ii/iii TM & k6 |
| Company: | Integrated Circuit System |
| Datasheet: | Download ICS9248SB-143 datasheet File size : 519 kB |
| Request For quote: | Find where to buy ICS9248SB-143
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS9248-143
Frequency Generator & Integrated Buffers for PENTIUM II/IIITM & K6
Recommended Application: 440BX, MX, VIA Apollo Pro 133, Apollo Pro Media or MVP4 style chip set, for Note book applications. Output Features: 4 - CPUs @ 2.5V/3.3V including 1 free running CPUCLK_F 9 - SDRAM @ 3.3V 7 - PCI @ 3.3V, including 1 free running PCICLK_F 1 - PCI Early @ 3.3V 1 - 48MHz, @ 3.3V fixed. 1 - 24/48MHz @ 3.3V 2 - REF @3.3V, 14.318MHz. Features: Up to 137MHz frequency support 97MHz to support high-end AMD processor. Support power management: CLK, PCI, stop and Power down Mode from I2C programming. Spread spectrum for EMI control (±.25% & 0 to -0.5% down spread). Uses external 14.318MHz crystal FS pins for frequency select Key Specifications: CPU Output Jitter @ 2.5V: <300ps CPU Output Jitter @ 3.3V: <250ps PCI Output Jitter @ 3.3V: <250ps CPU Output Skew @ 2.5V: <175ps CPU Output Skew @ 3.3V: <175ps PCI Output Skew @ 3.3V: <500ps PCI Early to PCI Skew @ 3.3V: typ = 3ns
Pin Configuration
VDDREF *SPREAD/REF0 GNDREF X1 X2 VDDPCI *CPU2.5_3.3#/PCICLK_F *FS3/PCICLK0 GNDPCI *SEL24_48#/PCICLK1 *SELPCIE_6#/PCICLK2 PCICLK3 PCICLK4 VDDPCI BUFFER IN GNDPCI PCICLK5 PCICLK6/PCICLK_E VDDCOR PCI_STOP# *PD# GND48 SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1/FS2* VDDLCPU CPUCLK_F CPUCLK0 GNDLCPU CPUCLK1 CPUCLK2 CLK_STOP# GNDSDR SDRAM_F SDRAM0 SDRAM1 VDDSDR SDRAM2 SDRAM3 GNDSDR SDRAM4 SDRAM5 VDDSDR SDRAM6 SDRAM7 VDD48 48MHz/FS0* 24_48MHz/FS1*
48-Pin SSOP and TSSOP
* Internal Pull-up Resistor of 120K to VDD
Functionality
FS3 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 CPU (MHz) 66.67 100.00 100.30 133.33 105.00 133.37 137.00 75.00 100.00 95.00 97.00 133.33 90.00 96.22 66.82 91.50 PCI (MHz) 33.33 33.33 33.43 33.33 35.00 33.34 34.25 37.50 33.33 31.67 32.33 33.33 30.00 32.07 33.41 30.50
Block Diagram
PLL2 48MHz /2 X1 X2 BUFFER IN CPUCLK_F PLL1 Spread Spectrum FS(0:3) SEL24_48#
4
LATCH STOP STOP
24_48MHz
2
XTAL OSC
REF[1:0]
3
CPUCLK [2:0]
8
SDRAM [7:0] SDRAM_F
4
POR
CLK_STOP# PCI_STOP# CPU2.5_3.3# SDATA SCLK PD# Control Logic Config. Reg.
PCI CLOCK DIVDER
STOP
6
PCICLK [5:0] PCICLK_F PCICLK_E
Pentium is a trademark of Intel Corporation I2C is a trademark of Philips Corporation
9248-143 Rev C 7/26/00
I C S reserves the right to make changes in the device data identified in t h i s publication without further notice. ICS advises its customers to o b t a i n the latest version of all device data to verify that any i n f o r m a t i o n being relied upon by the customer is current and accurate.
ICS9248-143
ICS9248-143
Pin Descriptions
PIN NUMBER 1 2 20 3, 9, 16, 33, 40, 44 4 5 6,14 7 8 10 11 17, 13, 12 15 18 19 21 22 28, 29, 31, 32, 34, 35, 37, 38 30, 36 23 24 25 26 27 39 41 42, 43, 45 46 47 48 P I N NA M E VDDREF S P R E A D 1,2 REF0 PCI_STOP# GND X1 X2 VDDPCI C P U 2 . 5 _ 3 . 3 # 1,2 PCICLK_F FS31,2 PCICLK0 SEL24_48#1,2 PCICLK1 SELPCIE_6#1,2 PCICLK2 PCICLK (5:3) BUFFER IN PCICLK6/PCICLK_E VDDCOR PD#1 GND48 SDRAM (7:0) VDDSDR SDATA SCLK 24_48MHz FS11, 2 48MHz FS01, 2 VDD48 SDRAM_F CLK_STOP# CPUCLK (2:0) CPUCLK_F VDDLCPU REF1 FS21, 2 TYPE PWR IN OUT IN PWR IN OUT PWR IN OUT IN OUT IN OUT IN OUT OUT IN OUT PWR IN PWR OUT PWR IN IN OUT IN OUT IN PWR OUT IN OUT OUT PWR OUT IN DESCRIPTION Ref, XTAL power supply, nominal 3.3V Active High Spread Spectrum enable input. Power-up default is "High", spreading is "on" 14.318 Mhz reference clock.This REF output is the STRONGER buffer for ISA BUS loads Halts PCICLK clocks at logic 0 level, when input low (In mobile mode, MODE=0) Ground Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Supply for PCICLK_F and PCICLK nominal 3.3V Indicates whether VDDLCPU is 2.5 or 3.3V. High=2.5V CPU, LOW=3.3V CPU. Latched Input. Free running PCI clock not affected by PCI_STOP# for power management. Frequency select pin. Latched Input. PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early) Selects either 24 or 48MHz when Low =48 MHz PCI clock output. Synchronous to CPU clocks with 1-4ns skew (CPU early) PCI Early or normal PCI select latch input. (for pin 18 power-up default is "High" early PCICLK.) PCICLK clock output. PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. PCI clock output or early PCI clock output selectable by SELPCIE_6# Power pin for the PLL core. 3.3V Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 4ms. Ground pin for the 24 & 48MHz output buffers & fixed PLL core. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Supply for SDRAM and CPU PLL Core, nominal 3.3V. Data input for I2C serial input, 5V tolerant input Clock input of I2C input, 5V tolerant input 24MHz or 48MHz output clock selectable by pin 10 Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input Power for 24 & 48MHz output buffers and fixed PLL core. Free running SDRAM clock output. Not affected by CPU_STOP# This asynchronous input halts CPUCLK, & SDRAM at logic "0" level when driven low. CPU clock outputs, powered by VDDLCPU Free running CPU clock. Not affected by the CPU_STOP# Supply for CPU clocks 2.5V 14.318 MHz reference clock. Frequency select pin. Latched Input
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9248-143
General Description
The ICS9248-143 is the single chip clock solution for Notebook designs using thE 440BX, MX, VIA Apollo Pro 133, Apollo Pro Media or MVP4 style chip set. It provides all necessary clock signals for such a system. Spread spectrum may be enabled through I2C programming. Spread spectrum typically reduces system EMI by 8dB to 10dB. This simplifies EMI qualification without resorting to board design iterations or costly shielding. The ICS9248-143 employs a proprietary closed loop design, which tightly controls the percentage of spreading over process and temperature variations.
Serial Configuration Command Bitmap
Bit Bit 7
Byte0: Functionality and Frequency Select Register (default = 0)
Description 0 - ±0.25% Spread Spectrum Modulation, Center Spread 1 - 0 to -0.5% Down Spread CPUCLK PCICLK Bit [2, 6:4] (MHz) (MHz) 0000 66.67 33.33 0001 100.00 33.33 0010 100.30 33.43 0011 133.33 33.33 0100 105.00 35.00 0101 133.37 33.34 0110 137.00 34.25 0111 75.00 37.50 1000 100.00 33.33 1001 95.00 31.67 1010 97.00 32.33 1011 133.33 33.33 1100 90.00 30.00 1101 96.22 32.07 1110 66.82 33.41 1111 91.50 30.50 0 - Frequency and Spread Spectrum are selected by hardware select, latched inputs 1 - Frequency is selected by Bit [2, 6:4]; Spread Spectrum is selected by bit 1 0 - Normal 1 - Spread Spectrum Enabled 0 - Running 1- Tristate all outputs PWD 1
Bit [2, 6:4]
Note1
Bit 3
0
Bit 1 Bit 0
1 0
Notes: 1, Default at Power-up will be for latched logic inputs to define frequency. Bit [2, 6:4] are default to 0011. 2, PWD = Power-Up Default
3
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