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Details, datasheet, quote on part number:ICS94211yF
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS94211
Programmable System Frequency Generator for PII/IIITM
Recommended Application: 440BX/VIA Apollo Pro133/ ALI 1631 style chipset. Output Features: · 2 - CPUs @2.5V · 1 - IOAPIC @ 2.5V · 13 - SDRAM @ 3.3V · 6 - PCI @3.3V, · 1 - 48MHz, @3.3V · 1 - 24MHz @ 3.3V · 2 - REF @3.3V, 14.318MHz. Features: · Programmable ouput frequency. · Programmable ouput rise/fall time. · Programmable PCICLK, PCICLK_F, SDRAM skew. · Real time system reset output · Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage. · Watchdog timer technology to reset system if over-clocking causes malfunction. · Uses external 14.318MHz crystal. · FS pins for frequency select Key Specifications: · CPU CPU: <175ps · SDRAM - SDRAM: <500ps · PCI PCI: <500ps · CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Pin Configuration
VDDREF *PCI_STOP/REF0 GND X1 X2 VDDPCI *MODE/PCICLK_F **FS3/PCICLK0 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDDPCI BUFFER_IN GND SDRAM12 SDRAM11 VDDSDR SDRAM10 SDRAM9 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDL IOAPIC REF1/FS2* GND CPUCLK0 CPUCLK1 VDDLCPU RESET# SDRAM0 GND SDRAM1 SDRAM2 VDDSDR SDRAM3 SDRAM4 GND SDRAM5 SDRAM6 VDDSDR SDRAM7 SDRAM8 VDD48 48MHz/FS0* 24MHz/FS1*
* Internal Pull-up Resistor of 120K to VDD ** Internal Pull-down resistor of 120K to GND
48-Pin 300mil SSOP
Functionality
FS3 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 80.00 75.00 83.31 66.82 103.00 112.01 68.01 100.23 120.00 114.99 109.99 105.00 140.00 150.00 124.00 132.99 PCICLK (MHz) 40.00 37.50 41.65 33.41 34.33 37.34 34.01 33.41 40.00 38.33 36.66 35.00 35.00 37.50 31.00 33.25
Block Diagram
PLL2 /2 X1 X2 BUFFER IN XTAL OSC
2
48MHz 24MHz IOAPIC REF(1:0) SDRAM (12:0) CPUCLK (1:0)
PLL1 Spread Spectrum
PCI CLOCK DIVDER
13
2
STOP
5
PCICLK (4:0) PCICLK_F RESET#
FS(3:0) 4 MODE PCI_STOP# SDATA SCLK
Control Logic Config. Reg.
0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
94211 Rev B 01/18/02
I C S reserves the right to make changes in the device data identified in t h i s publication without further notice. ICS advises its customers to o b t a i n the latest version of all device data to verify that any i n f o r m a t i o n being relied upon by the customer is current and accurate.
ICS94211
ICS94211
General Description
The ICS94211 is a single chip clock solution for desktop designs using the BX/Apollo Pro133/ALI 1631 style chipset. It provides all necessary clock signals for such a system. The ICS94211 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
Pin Configuration
PIN NUMBER 1 2 3, 9, 16, 22, 33, 39, 45 4 5 6, 14 7 P I N NA M E VDDREF REF0 PCI_STOP# GND X1 X2 VDDPCI PCICLK_F MODE1, 2 FS3 8 13, 12, 11, 10 PCICLK0 PCICLK (4:1)
1
TYPE PWR OUT IN PWR IN OUT PWR OUT IN IN OUT OUT IN OUT PWR I/O IN OUT IN OUT IN PWR OUT PWR OUT OUT OUT IN OUT PWR
DESCRIPTION Ref, XTAL power supply, nominal 3.3V 14.318 Mhz reference clock. Halts PCICLK(0:4) clocks at logic 0 level, when input low (In mobile mode, MODE=0) Ground Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (36pF) Supply for PCICLK_F and PCICLK (0:4), nominal 3.3V Free running PCI clock not affected by PCI_STOP# for power management. Pin 7 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. Frequency select pin. Latched Input. Internal Pull-down to GND PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew (CPU early) PCI clock outputs. Syncheronous to CPU clocks with 1-48ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset) Supply for SDRAM (0:12) and CPU PLL Core, nominal 3.3V. Data input for I2C serial input, 5V tolerant input Clock input of I2C input, 5V tolerant input 24MHz output clock Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input Power for 24 & 48MHz output buffers and fixed PLL core. R e a l t i m e s y s t e m r e s e t s i g n a l f o r f r e q u e n cy r a t i o c h a n g e o r w a t c h d o g timmer timeout. This signal is active low. Supply for CPU clocks, either 2.5V or 3.3V nominal CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low Free running CPU clock. Not affected by the CPU_STOP# 14.318 MHz reference clock. Frequency select pin. Latched Input IOAPIC c l o c k o u t p u t . 1 4 . 3 1 8 M H z P ow e r e d b y V D D L . Supply for IOAPIC, either 2.5 or 3.3V nominal
15 BUFFER IN 17, 18, 20, 21, 28, 29, 31, 32, 34, 35, 37, 38, SDRAM (12:0) 40 19, 30, 36 VDDSDR 23 24 25 26 27 41 42 43 44 46 47 48 SDATA SCLK 24MHz FS11, 2 48MHz FS01, 2 VDD48 RESET VDDLCPU CPUCLK1 CPUCLK0 REF1 FS21, 2 I OA P I C VDDL
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
2
ICS94211
General I2C serial interface information for the ICS94211 How to Write:
Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending Byte 0 through Byte 20 (see Note) ICS clock will acknowledge each byte one at a time Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends Byte 0 through byte 8 (default) ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). Controller (host) will need to acknowledge each byte Controller (host) will send a stop bit
Ho w to Write:
Control l e r (Host) S t art Bit A ddres s D2(H ) Dum m y Command Code A CK Dum m y Byte Count A CK Byte 0 A CK Byte 1 A CK Byte 2 A CK Byte 3 A CK Byte 4 A CK Byte 5 A CK Byte 6 A CK I CS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
A CK
ACK Byte Count ACK Byte 0 ACK Byte 1 ACK Byte 2 ACK Byte 3 ACK Byte 4 ACK Byte 5 ACK Byte 6 ACK If 7H has been written to B6 ACK Byte 7
B y t e 18 A CK B y t e 19 A CK B y t e 20 A CK S t op Bit
*See notes on the following page.
If 12H has been written to B6 ACK If 13H has been written to B6 ACK If 14H has been written to B6 ACK Stop Bit
Byte18 Byte 19 Byte 20
3
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