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Details, datasheet, quote on part number:ICS94215yF
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| Part: | ICS94215yF |
| Category: | Timing Circuits => Clock Synthesizers => Motherboards |
| Description: | Programmablefrequency Generator And Integrated Buffers Amd K7 |
| Company: | Integrated Circuit System |
| Datasheet: | Download ICS94215yF datasheet File size : 151 kB |
| Request For quote: | Find where to buy ICS94215yF
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS94215
Programmable System Clock Chip for AMD - K7TM Processor
Recommended Application: VIA KX/KT133 style chipset Output Features: · 1 - Differential pair open drain CPU clocks · 1 - CPU clock @ 3.3V · 13 - SDRAM @ 3.3V · 6 - PCI @3.3V, · 1 - 48MHz, @3.3V fixed. · 1 - 24/48MHz @ 3.3V · 2 - REF @3.3V, 14.318MHz. Features: · Programmable ouput frequency. · Programmable ouput rise/fall time. · Programmable PCI_F and PCICLK skew. · Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage. · Watchdog timer technology to reset system if over-clocking causes malfunction. · Uses external 14.318MHz crystal. · FS pins for frequency select
Pin Configuration
VDD1 REF0/CPU_STOP#* GND X1 X2 VDD2 *MODE/PCICLK_F *FS3/PCICLK0 GND *SEL24_48#/PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDD2 BUFFER IN GND SDRAM11 SDRAM10 VDD3 SDRAM9 SDRAM8 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF1/FS2* GND CPUCLK GND CPUCLKC0 CPUCLKT0 VDDCPU PD#* SDRAM_OUT GND SDRAM0 SDRAM1 VDD3 SDRAM2 SDRAM3 GND SDRAM4 SDRAM5 VDD3 SDRAM6 SDRAM7 VDD4 48MHz/FS0* 24/48MHz/FS1*
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectr um 48MHz 24_48MHz
Functionality
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 90.00 95.00 101.00 102.00 100.90 103.00 105.00 100.00 107.00 109.00 110.00 111.00 113.00 115.00 117.00 133.30 PCICLK (MHz) 30.00 31.67 33.67 34.00 33.57 34.33 35.00 33.33 35.67 36.33 36.67 37.00 37.67 38.33 39.00 33.33
REF (1:0) CPUCLK
CPU DIVDER Stop
CPUCLKC0 CPUCLKT0
SEL24_48# SDATA SCLK FS (3:0) PD# CPU_STOP# BUFFER IN
0442C--07/03/02
Control Logic Config. Reg.
PCI DIVDER
PCICLK (4:0) PCICLK_F
SDRAM DRIVER
SDRAM (11:0) SDRAM_OUT
ICS94215
ICS94215
Pin Descriptions
PIN NUMBER 1 2 CPU_STOP#1, 2 3,9,16,22, 33,39,45, 47 4 5 6,14 7 MODE1, 2 8 10 11, 12, 13 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 35,37,38 19,30,36 23 24 25 26 27 40 41 42 43 44 46 48 FS3 PCICLK0 SEL24_48#1, 2 PCICLK1 PCICLK(2:4) BUFFER IN SDRAM (11:0) VDD3 SDATA SCLK 24_48MHz FS1 FS0
1, 2 1, 2
PIN NAME VDD1 REF0
TYPE DESCRIPTION P W R Ref (0:2), XTAL power supply, nominal 3.3V 14.318 Mhz reference clock.This REF output is the OUT STRONGER buffer for ISA BUS loads This asynchronous input halts CPUCLKT, CPUCLKC & at logic IN "0" level when driven low. PWR IN OUT PWR OUT IN IN OUT IN OUT OUT IN OUT PWR IN IN OUT IN OUT IN PWR OUT IN PWR OUT OUT OUT OUT IN Ground Cr ystal input, has inter nal load cap (36pF) and feedback resistor from X2 Cr ystal output, nominally 14.318MHz. Has inter nal load cap (36pF) Supply for PCICLK_F and PCICLK (0:4), nominal 3.3V Free running PCI clock not affected by PCI_STOP# for power management. Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile Mode. Latched Input. Frequency select pin. Latched Input. Internal Pull-down to GND PCI clock output Logic input to select 24 or 48MHz for pin 25 output PCI clock output. PCI clock outputs. Input to Fanout Buffers for SDRAM outputs. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset). Supply for SDRAM (0:12) nominal 3.3V. Data input for I2C serial input, 5V tolerant input Clock input of I2C input, 5V tolerant input 24MHz/48MHz clock output Frequency select pin. Latched Input. 48MHz output clock Frequency select pin. Latched Input Power for 24 & 48MHz output buffers and fixed PLL core. Reference clock for SDRAM zero delay buffer Powers down chip, active low Supply for CPU clock 3.3V "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. "Complementory" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. 3.3V CPU clock output powered by pin 42 14.318 MHz reference clock. Frequency select pin. Latched Input
GND X1 X2 VDD2 PCICLK_F
48MHz
1, 2
VDD4 SDRAM_OUT PD#1, 2 VDDCPU CPUCLKT0 CPUCLKC0 CPUCLK REF1 FS21, 2
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
0442C--07/03/02
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ICS94215
General Description
The ICS94215 is a main clock synthesizer chip for AMD-K7 based systems with VIA style chipset. This provides all clocks required for such a system. The ICS94215 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/ enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
Mode Pin - Power Management Input Control
MODE, Pin 7 (Latched Input) 0 1 Pin 2 CPU_STOP# (Input) REF0 (Output)
0442C--07/03/02
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