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Details, datasheet, quote on part number:ICS94222yFT
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| Part: | ICS94222yFT |
| Category: | Timing Circuits => Clock Synthesizers => Motherboards |
| Description: | Frequencygenerator And Integrated Buffers For Celeron, Pii/iii |
| Company: | Integrated Circuit System |
| Datasheet: | Download ICS94222yFT datasheet File size : 430 kB |
| Request For quote: | Find where to buy ICS94222yFT
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS94222
Advance Information
Programmable System Frequency Generator for PII/IIITM
Recommended Application: BX, Appollo Pro 133 type of chip set. Output Features: · 3 - CPUs @2.5V, up to 166MHz. · 17 - SDRAM @ 3.3V, up to 166MHz. · 7 - PCI @3.3V · 2 - IOAPIC @ 2.5V · 1 - 48MHz, @3.3V fixed. · 1 - 24MHz @ 3.3V · 2 - REF @3.3V, 14.318MHz. Features: · Programmable ouput frequency. · Programmable ouput rise/fall time. · Programmable PCI_F and PCICLK skew. · Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage. · Watchdog timer technology to reset system if over-clocking causes malfunction. · Uses external 14.318MHz crystal. · FS pins for frequency select Key Specifications: · CPU CPU: <175ps · SDRAM - SDRAM: <500ps · PCI PCI: <500ps · CPU-SDRAM: <500ps · CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Pin Configuration
AVDD *FS2/REF1 *PCI_STOP#/REF0 GND X1 X2 VDD *MODE/PCICLK_F *FS3/PCICLK0 GND PCICLK1 PCICLK2 PCICLK3 PCICLK4 VDD PCICLK5 BUFFERIN SDRAM11 SDRAM10 VDD SDRAM9 SDRAM8 GND SDRAM15 SDRAM14 GND SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDDL IOAPIC0 IOAPIC_F GND CPUCLK_F CPUCLK0 VDDL CPUCLK1 GND CLK_STOP* SDRAM_F VDDSDR SDRAM0 SDRAM1 GND SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDD SDRAM6 SDRAM7 GND SDRAM12 SDRAM13 AVDD48 24MHz/FS0* 1 48MHz/FSI*
56-Pin SSOP
* Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
Functionality Block Diagram
PLL2
÷2
ICS94222
CPU (MHz) 80.00 75.00 83.31 66.9 103.00 112.01 68.01 100.7 120.00 114.99 109.99 105.00 140.00 150.00 124.00 133.9
48MHz 24MHz IOAPIC_F
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
X1 X2
XTAL OSC
STOP
IOAPIC0
2
REF [1:0] CPUCLK_F CPUCLK (1:0)
PLL1 Spread Spectrum FS (3:0) MODE
POR LATCH
PCI CLOCK DIVDER
1
STOP
STOP
6
PCICLK (5:0) PCICLK_F
CLK_STOP# PCI_STOP# SCLK SDATA BUFFERIN Control Logic Config. Reg.
STOP
16
SDRAM (15:0) SDRAM_F
PCICLK (MHz) 40.00 37.50 41.65 33.45 34.33 37.34 34.01 33.57 40.00 38.33 36.66 35.00 35.00 37.50 31.00 33.25
9 4 2 2 2 Rev - 5/10/01 T h i s document is confidential and should not be released w i t h o u t written consents from ICS.
ADVANCE INFORMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice.
ICS94222
Advance Information
Pin Configuration
PIN NUMBER 1 2 P I N NA M E AVDD REF1 FS21 REF0 P C I _ S TO P # 1 TYPE PWR OUT IN OUT IN PWR IN OUT PWR OUT IN IN OUT OUT IN IN IN OUT IN OUT IN PWR DESCRIPTION Analog power supply 3.3V 14.318 MHz reference clock output L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D 14.318MHz reference clock output Halts PCICLK [5:1] at logic "0" level when low. (in mobile, MODE=0) Ground. 14.318MHz input. Has internal load cap, (nominal 33pF). Crystal output. Has internal load cap (33pF) and feedback resistor to X1 Nominal 3.3V power supply, see power groups for function. F r e e r u n n i n g B U S c l o c k n o t a f e c t e d b y P C I _ S TO P # Latched input for MODE select. Converts pin 3 to PCI_STOP# when low for power management. Latched frequency select input, pull-down F r e e r u n n i n g B U S c l o c k n o t a f e c t e d b y P C I _ S TO P # PCI Clock Outputs. Input for Buffers Serial data in for serial config port. (I2C) Clock input for serial config port. (I2C) 24MHz clock output for Super I/O or FD. L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D 48MHz clock output for USB, 2X strength. L a t c h e d f r e q u e n cy s e l e c t i n p u t . H a s p u l l - u p t o V D D Analog power supply 3.3V
3
4, 10, 23, 26, 34, 42, GND 48, 53 5 6 7, 15, 20, 37, 45 8 X1 X2 VDD PCICLK_F MODE1 FS31 PCICLK0 PCICLK (5:1) BU F F E R I N SDATA SCLK 24MHz 30 FS0 29 31 24, 25, 32, 33, 18, 19, 21, 22, 35, 36, 38, 39, 40, 41, 43, 44 46 47 50, 56 55 49, 51 52 54
1
9 16, 14, 13, 12, 11 17 27 28
48MHz FS11 AVDD48
SDRAM (15:0)
OUT
SDRAM clocks
SDRAM_F C L K _ S TO P # VDDL I OA P I C 0 CPUCLK (1:0) CPUCLK_F I OA P I C _ F
OUT IN PWR OUT OUT OUT OUT
Free running SDRAM clock Not affected by CPU_STOP# Halts CPUCLKs, IOAPIC0, SDRAMs clocks at logic "0" level when low. CPU and IOAPIC clock buffer power supply, 2.5V nominal. IOAPIC clock output. (14.318 MHz) Poweredby VDDL CPU Output clocks. Powered by VDDL (60 or 66.6MHz) Free running CPU output clock. Not affected ty the CLK_STOP#. Freerunning IOAPIC clock output. Not affected by the CLK_STOP# (14.31818 MHz) Powered by VDDL
Notes: 1: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
T h i s document is confidential and should not be released w i t h o u t written consent from ICS.
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ICS94222
Advance Information
General Description
The ICS94222 is a single chip clock solution for desktop designs using the BX/Apollo Pro133/ALI 1631 style chipset. It provides all necessary clock signals for such a system. The ICS94222 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
Mode Pin - Power Management Input Control
MODE (Latched Input) 0 1 Pin 3 PCI_STOP# (Input) REF0 (Output)
Power Groups
AVDD48 = 48MHz, Fixed PLL AVDD = CPU PLL, XTAL
T h i s document is confidential and should not be released w i t h o u t written consent from ICS.
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