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Details, datasheet, quote on part number:ICS94225
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS94225
Preliminary Product Preview
AMD-K7TM System Clock Chip
Recommended Application: AMD 750/760 style chipset Output Features: · 3 differential pair open drain CPU clocks (1.5V external pull-up; up to 150MHz achieviable through I2C) · 2 - AGPCLK @ 3.3V · 8 - PCI @3.3V, including 1 free running · 1 - 48MHz @ 3.3V · 1 - 24/48MHz @ 3.3V · 2- REF @3.3V, 14.318MHz. Features: · Programmable ouput frequency · Programmable ouput rise/fall time · Programmable group skew · Real time system reset output · Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage · Watchdog timer technology to reset system if over-clocking causes malfunction · Uses external 14.318MHz crystal
Pin Configuration
**FS0/REF0 **FS1/REF1 GNDREF X1 X2 GNDPCI PCICLK_F PCICLK0 VDDPCI PCICLK1 PCICLK2 GNDPCI PCICLK3 PCICLK4 VDDPCI PCICLK5 PCICLK6 VDDAGP AGP0 AGP1 GNDAGP VDD48 48MHz SEL24_48#/24-48MHz 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VDDREF GNDSD SDRAM_OUT VDDSD RESERVED CPUCLKC2 CPUCLKT2 GNDCPU CPUCLKC1 CPUCLKT1 GND CPUCLKC0 CPUCLKT0 RESET# VDD GND PCI_STOP# CPU_STOP# PD# SPREAD# FS2* SDATA SCLK GND48
48-Pin 300mil SSOP
* Internal 120K pullup resistor on indicated inputs ** Internal 240K pullup resistor on indicated inputs
Block Diagram Functionality
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz 24_48MHz
FS2 0 0 0 0 1 1 1 1
FS1 0 0 1 1 0 0 1 1
FS0 0 1 0 1 0 1 0 1
REF (1:0)
CPU DIVDER
Stop
3 3
CPUCLKT (2:0) CPUCLKC (2:0) SDRAM_OUT
SDRAM DIVDER
SEL24_48# SDATA Control SCLK FS (2:0) PD# PCI_STOP# CPU_STOP# SPREAD# Config. Reg. Logic
AGP DIVDER
2
PCI DIVDER
Stop
7
PCICLK (6:0) PCICLK_F AGP (1:0)
C P U, SDRAM 133.33 95 100.99 115 100.7 103 105 110
ICS94225
PCI 33.33 31.67 33.66 38.33 33.57 34.33 35.00 36.67
AG P 66.67 63.33 67.33 76.67 67.13 68.67 70.00 73.33
Power Groups
VDD48, GND48 = 48MHz, PLL2 VDDREF, GNDREF= REF, X1, X2 VDD, GND = PLL Core
94225 Rev A 5/10/01 Third party brands and names are the property of their respective owners.
P R O D U C T PREVIEW documents contain information on new p r o d u c t s in the sampling or preproduction phase of development. C h a r a c t e r i s t i c data and other specifications are subject to change w i t h o u t notice.
ICS94225
Preliminary Product Preview
General Description
The ICS94225 is a main clock synthesizer chip for AMD-K7 based systems with AMD 750/760 style chipsets. This provides all clocks required for such a system. The ICS94225 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
Pin Descriptions
PIN NUMBER 2,1 3, 6, 21, 25, 33, 38, 41, 47 4 5 7 17, 16, 14, 13, 11, 10, 8 9, 15 18 20, 19 34 22 23 24 26 27 28 29 30 31 32 35 46 44 42, 39, 36 43, 40, 37 45 48 PIN NAME FS (1:0) REF (1:0) GND X1 X2 PCICLK_F PCICLK (6:0) VDDPCI VDDAGP AGP (1:0) VDD VDD48 48MHz SEL24-48# 24-48MHz SCLK SDATA FS2 SPREAD# PD# CPU_STOP# PCI_STOP# TYPE IN OUT PWR IN OUT OUT OUT PWR PWR OUT PWR PWR OUT IN OUT IN I/O IN IN IN IN IN DESCRIPTION Frequency Select pins, has pull-up to VDD 14.318MHz clock output Ground XTAL_IN 14.318MHz Crystal input, has internal 33pF load cap and feed back resistor from X2 XTAL_OUT Crystal output, has internal load cap 33pF Free Running PCI output. Not affected by the PCI_STOP# input. PCI clock outputs. TTL compatible 3.3V Power for PCICLK outputs, nominally 3.3V Power for AGP outputs, nominally 3.3V AGP outputs defined as 2X PCI. These may not be stopped. Isolated power for core, nominally 3.3V Power for 48MHz and 24MHz outputs nominally 3.3V 48MHz output Selects 24 or 48MHz output for pin 24 Low = 48MHz High = 24MHz Fixed clock out selectable through SEL24-48# Clock pin of I2C circuitry 5V tolerant Data pin for I2C circuitry 5V tolerant Frequency Select pin, has pull-up to VDD Enables Spread Spectrum feature when LOW. Down Spread 0.5% modulation frequency =50KHz Powers down chip, active low. Internal PLL & all outputs are disabled. Halts CPUCLKs. CPUCLKT is driven LOW wheras CPUCLKC is driven HIGH when this pin is asserted (Active LOW). Halts PCI Bus at logic "0" level when driven low. PCICLK_F is not affected by this pin
RESET#
SDRAM_OUT RESERVED CPUCLKT (2:0) CPUCLKC (2:0) VDDSD VDDREF
OUT
OUT N/C OUT OUT PWR PWR
Real time system reset signal for watchdog tmer timeout. This signal is active low.
Reference clock for SDRAM zero delay buffer Future CPU power rail "True" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. "Complementory" clocks of differental pair CPU output. These open drain outputs need an external 1.5V pull_up. Power for SDRAM_OUT pin. Norminally 3.3V Power for REF, X1, X2, nominally 3.3V
Third party brands and names are the property of their respective owners.
2
ICS94225
Preliminary Product Preview
Byte 1: Reserved Active/Inactive Register (1= enable, 0 = disable)
Byte 2: Reserved, Active/Inactive Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
Byte 3: Reserved Active/Inactive Register (1= enable, 0 = disable)
Byte 4: Clock Control Register (1= enable, 0 = disable)
BIT
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
PIN#
-
PWD
1 1 1 1 1 1 1 1
DESCRIPTION
(Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved) (Reserved)
BIT
7 6 5 4 3 2 1 0
PIN# PWD
1 23 22 20 19 42, 43 39, 40 36, 37 1 1 1 1 1 1 1 1 REF0
DESCRIPTION
24MHz/48MHz USB0 AGP1 AGP0 CPUCLKC/T2 CPUCLKC/T1 CPUCLKC/T0
Byte 5: PCI Clock Control Register (1= enable, 0 = disable)
BIT
7 6 5 4 3 2 1 0
Notes:
PIN# PWD
2 17 16 14 13 11 10 8 1 1 1 1 1 1 1 1 REF1
DESCRIPTION
PCICLK6 PCICLK5 PCICLK4 PCICLK3 PCICLK2 PCICLK1 PCICLK0
1. Inactive means outputs are held LOW and are disabled from switching. 2. Latched Frequency Selects (FS#) will be inverted logic load of the input frequency select pin conditions.
Third party brands and names are the property of their respective owners.
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