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Details, datasheet, quote on part number:ICS94229yF-T
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS94229
Advance Information
Programmable System Clock Chip for AMD - K7TM processor
Recommended Application: VIA KT266 style chipset Output Features: · 1 - Differential pair open drain CPU clocks @ 2.5V · 1 - Differential pair push-pull CPU clocks @ 2.5V · 11 - PCI including 1 free running and 1 early @ 3.3V · 1 - 48MHz, @ 3.3V fixed · 1 - 24/48MHz @ 3.3V · 3 - REF @ 3.3V, 14.318MHz. Features: · Programmable output frequency. · Programmable output rise/fall time. · Programmable slew and skew control for CPUCLK, PCICLK, AGP, REF, 48MHz and 24_48MHz. · Real time system reset output. · Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage. · Watchdog timer technology to reset system if over-clocking causes malfunction. · Uses external 14.318MHz crystal. Skew Specifications: · CPU - CPU: <175ps · PCI - PCI: <500ps · CPU (early - PCI: min=1.0ns, max=2.0ns · CPU cycle to cycle jitter: <250ps
Pin Configuration
VDDREF GND X1 X2 AVDD48 *FS2/48MHz *FS3/24_48MHz GND *WDEN/PCICLK_F *SEL24_48#/PCICLK0 PCICLK1 GND PCICLK2 PCICLK3 VDDPCI PCICLK4 PCICLK5 PCICLK6 GND PCICLK7 PCILCK8 PCICLK9_E VDDPCI SRESET# 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 REF0/FS0* REF1/FS1* REF_F RATIO AGP_STOP#* GND CPUCLKT0 CPUCLKC0 VDDL CPUCLK_CST0 CPUCLK_CSC0 GND CPU_STOP#* PCI_STOP#* PD#* AVDD AGND SDATA SCLK GND AGP2 AGP1 AGP0 VDDAGP
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD
Block Diagram
PLL2 /2 X1 X2 XTAL OSC PLL1 Spread Spectrum 48MHz (1:0) 24_48MHz
Functionality
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU (MHz) 233.33 220.00 210.00 200.00 190.00 180.00 170.00 150.00 140.00 120.00 110.00 66.67 200.00 166.67 100.00 133.33 AG P (MHz) 77.78 73.33 70.00 66.67 76.00 72.00 68.00 75.00 70.00 60.00 66.00 66.67 66.67 66.67 66.67 66.67 PCICLK (MHz) 38.88 36.67 35.00 33.33 38.00 36.00 34.00 37.50 35.00 30.00 33.00 33.33 33.33 33.33 33.33 33.33
2
2
REF (1:0) REF_F
CPU DIVDER
Stop
CPUCLKT0 CPUCLKC0 CPUCLK_CST0 CPUCLK_CSC0 PCICLK9_E
CPU DIVDER
Stop
SEL24_48# SDATA SCLK FS (3:0) PD# PCI_STOP# CPU_STOP# AGP_STOP# Control Logic
AGP DIVDER Stop
3
PCI DIVDER
Stop
9
PCICLK (8:0) PCICLK_F AGP (2:0) SRESET# RATIO
Config. Reg.
94229 Rev - 05/31/01 Third party brands and names are the property of their respective owners.
A DVA N C E INFORMATION documents contain information on products i n the formative or design phase development. Characteristic data and o t h e r specifications are design goals. ICS reserves the right to change or d i s c o n t i n u e these products without notice.
ICS94229
ICS94229
Advance Information
Pin Descriptions
PIN NUMBER 1, 15, 23, 25, 2, 8, 12, 19, 29, 37, 43 3 4 5 6 7 9 10 21, 20, 18, 17, 16, 14, 13, 11 22 24 28, 27, 26 30 31 32 33 34 35 36 38 39 40 42 41 44 45 46 47 48 P I N NA M E VDD GND X1 X2 AVDD48 FS21, 2 48MHz FS31, 2 24_48MHz WDEN PCICLK_F SEL24_48#1, 2 PCICLK0 PCICLK (8:1) PCICLK9_E SRESET#1 AGP (2:0) SCLK SDATA AGND AVDD PD# PCI_STOP# CPU_STOP#1, 2 CPUCLK_CSC0 CPUCLK_CST0 VDDL CPUCLKT0 CPUCLKC0 AGP_STOP# RATIO REF_F FS11, 2 REF1 FS01, 2 REF0 TYPE PWR PWR IN OUT PWR IN OUT IN OUT IN OUT IN OUT OUT OUT OUT OUT IN I/O PWR PWR IN IN IN OUT OUT PWR OUT OUT IN OUT OUT IN OUT IN OUT DESCRIPTION Power supply, nominal 3.3V Ground Crystal input, has internal load cap (36pF) and feedback resistor from X2 Crystal output, nominally 14.318MHz. Has internal load cap (36pF) Power supply, nominal 3.3V Frequency select pin. Latched Input 48MHz output clock Frequency select pin. Latched Input 24 or 48MHz clock output Hardware enable of watch dog circuit. Default safe frequency is 100MHz. Free running PCI clock not affected by PCI_STOP# for power management. Logic input to select 24 or 48MHz for pin 7 output PCI clock output PCI clock outputs. Early PCI clock. Leads general PCI clocks by 2ns. Can be stopped by PCI_STOP#. Real time system reset signal for watchdog tmer timeout. This signal is active low. AGP clock outputs Clock input of I2C input, 5V tolerant input Data pin for I2C circuitry 5V tolerant Analog ground Power supply, nominal 3.3V Asynchronous active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. Stops all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low This asynchronous input halts CPUCLKT, CPUCLKC & CUCLKC_CS clocks at logic "0" level when driven low. "Complementary" clock of differential pair CPU output. These push-pull outputs need an external 1.5V pull-up (push-pull) "True" clock of differential pair CPU output. These push-pull outputs need an external 1.5V pull-up (push-pull). Power supply for CPUCLKs, nominal 2.5V "True" clock of differential pair CPU output. These open drain outputs need an external 1.5V pull-up (open drain). "Complementary" clock of differential pair CPU output. These open drain outputs need an external 1.5V pull-up (open drain). Stops all AGP clocks at logic 0 level, when input low Outputs a "0" for 100MHz or "1" for 133MHz to the South Bridge 14.318 MHz free running reference clock., not afftected by REF_STOP# Frequency select pin. Latched Input 14.318 MHz reference clock. Frequency select pin. Latched Input 14.318 MHz reference clock.
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
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ICS94229
Advance Information
General Description
The ICS94229 is a main clock synthesizer chip for AMD-K7 based systems with VIA KT266 style chipset. This provides all clocks required for such a system. The ICS94229 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
SRESET# Signal Description
The SRESET# signal from ICS94229 system clock generator is a real time active low pulse that can be used to reset the system. The Open-Drain Nch output Reset# pin needs to be tied to the system reset line which has a pull-up resistor. When activated, the SRESET# output will be driven to a low with a 288ms pulse width.
Third party brands and names are the property of their respective owners.
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