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Details, datasheet, quote on part number:ICS94235yFT
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS94235
Programmable System Clock Chip for AMD - K7 processor
Recommended Application: ALI 1647 style chipset Output Features: · 1 - Differential pair open drain CPU clocks · 1 - Single-ended open drain CPU clock · 13 - SDRAM @ 3.3V · 7 - PCI @ 3.3V · 2 - AGP @ 3.3V · 1 - 48MHz, @3.3V · 1 - REF @ 3.3V, (selectable strength) through I2C Features: · Programmable ouput frequency · Programmable ouput rise/fall time · Programmable CPU, SDRAM, PCI and AGP skew · Real time system reset output · Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage · Watchdog timer technology to reset system if over-clocking causes malfunction · Uses external 14.318MHz crystal Skew Specifications: · CPUT - CPUC: <250ps · PCI - PCI: <500ps · CPU - SDRAM: <350ps · SDRAM - SDRAM: <250ps · AGP - AGP: <250ps · AGP - PCI: <750ps · CPU - PCI: <3ns
Pin Configuration
RESET# *PD# GND X1 X2 AVDD **FS0/REF0 VDD **FS1/AGP0 AGP1 GND *FS2/PCICLK_F PCICLK0 PCICLK1 PCICLK2 GND VDD *MODE/PCICLK3 PCICLK4 PCICLK5 AVDD48 **FS3/48MHz GND SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 GND CPUCLKT0 CPUCLKC0 CPUCLKT1 SDATA SDRAM0 SDRAM1 GND VDD SDRAM2 SDRAM3 SDRAM4 SDRAM5 VDD GND SDRAM6 SDRAM7 SDRAM8 SDRAM9 GND VDD SDRAM10(PCI_STOP#)* SDRAM11 SDRAM12
48-Pin 300mil SSOP & 240mil TSSOP package
Notes: REF0 could be 1X or 2X strength controlled by I2C. * Internal Pull-up Resistor of 120K to VDD * * Internal pull-down of 120K to GND.
Block Diagram
PLL2 48MHz
Functionality
FS 3 0 0 0 0 0 0 0 0 1 1 1 1 1 0 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CP U S D RA M 6 6. 66 6 6. 66 6 6. 66 10 0. 00 10 0. 00 6 6. 66 10 0. 00 10 0. 00 10 0. 00 13 3. 33 12 0. 00 12 0. 00 13 3. 33 10 0. 00 13 3. 33 13 3. 33 9 0. 00 9 0. 00 10 0. 90 10 0. 90 10 0. 00 6 6. 66 10 0. 00 10 0. 00 10 0. 00 13 3. 33 12 6. 00 12 6. 00 13 3. 33 10 0. 00 13 3. 33 13 3. 33 P CI 3 3. 33 3 3. 33 3 3. 33 3 3. 33 3 3. 33 3 0. 00 3 3. 33 3 3. 33 3 0. 00 3 3. 63 3 3. 33 3 3. 33 3 3. 33 3 1. 50 3 3. 33 3 3. 33 AG P 66. 66 66. 66 66. 66 66. 66 66. 66 60. 00 66. 66 66. 66 60. 00 67. 27 66. 66 66. 66 66. 66 63. 00 66. 66 66. 66
X1 X2
XTAL OSC PLL1 Spread Spectrum
REF0
CPU DIVDER
2
CPUCLKT (1:0) CPUCLKC0
SDRAM DIVDER
Stop
13
SDRAM (12:0)
SDATA SCLK FS (3:0) PD# PCI_STOP# MODE
Control Logic Config. Reg.
PCI DIVDER Stop
6
PCICLK (5:0) PCICLK_F
AGP DIVDER
Stop
2
AGP (1:0) RESET#
Power Groups
AVDD = Xtal, Core PLL AVDD48 = 48MHz, Fixed PLL
9 4 2 3 5 Rev A 01/17/02 Third party brands and names are the property of their respective owners.
ICS94235
ICS94235
Pin Descriptions
PI N NUMBER 1 PI N NAME R E S E T# T Y PE OUT D E S C R I PT I ON R eal time system reset signal for frequency value or watchdog timmer timeout. This signal is active low. A s y n ch ro n o u s active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down will not be greater than 3ms. C ry s tal input,nominally 14.318MHz. C ry s tal output, nominally 14.318MHz. G ro u n d pins P o w er supply pins, nominal 3.3V A n alo g power supply pin, nominal 3.3V F req u en cy select pin. 1 4 .3 1 8 MHz reference clock. F req u en cy select pin. A G P outputs defined as 2X PCI. These may not be stopped. A G P outputs defined as 2X PCI. These may not be stopped. F ree running PCICLK not stoped by PCI_STOP# F req u en cy select pin. P C I clock outputs. P C I clock output. F u n ctio n select pin, 1=Desktop Mode, 0=Mobile Mode. A n alo g power supply pin, nominal 3.3V F req u en cy select pin. 4 8 M H z output clock C lo ck input of I C input, 5V tolerant input S to p s all PCICLKs besides the PCICLK_F clocks at logic 0 level, when input low S D R A M clock output. S D R A M clock outputs. D ata pin for I C circuitry 5V tolerant " Tru e" clocks of differential pair CPU outputs. These open drain outputs need an external 1.5V pull-up. "Complementory" clocks of differential pair CPU outputs. This open drain output need an external 1.5V pull-up.
2 2
2 4 5 3, 11, 16, 23, 29, 34, 41, 48 8 , 17, 28, 35, 40 6 7 9 10 12 20, 19, 15, 14, 13 18 21 22 24 27 2 5 , 26, 30, 31, 32, 33, 36, 37, 38, 39, 42, 43 44 45, 47 46
PD# X1 X2
1
IN IN OUT P WR P WR P WR IN OUT IN OUT OUT OUT IN OUT OUT IN P WR IN OUT IN
1
GND VDD AVDD FS0 REF0
2, 3
FS1 AGP0 AGP1 P C IC LK _ F FS2 P C I C LK (5:4) (2:0) PCICLK3 MODE A V D D 48 FS3 48MHz S C LK P C I _ S TO P # SDRAM10 S D RA M (12:11, 9:0 ) S D A TA C P U C LK T (1:0) C P U C LK C 0
2, 3 1, 3 1, 3
2, 3
IN OUT OUT I/O OUT OUT
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Internal pull-down resistor of 120K to GND. 3: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
Third party brands and names are the property of their respective owners.
2
P R O D U C T PREVIEW documents contain information on new p r o d u c t s in the sampling or preproduction phase of development. C h a r a c t e r i s t i c data and other specifications are subject to change w i t h o u t notice.
ICS94235
General Description
The ICS94235 is a main clock synthesizer chip for AMD-K7 based systems with ALI 1647 style chipset. This provides all clocks required for such a system. The ICS94235 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
Mode Pin - Power Management Input Control
MODE, Pin 18 (Latched Input) 0 1 Pin 27 PCI_STOP# (Input) SDRAM10 (Output)
Third party brands and names are the property of their respective owners.
3
P R O D U C T PREVIEW documents contain information on new p r o d u c t s in the sampling or preproduction phase of development. C h a r a c t e r i s t i c data and other specifications are subject to change w i t h o u t notice.
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