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Details, datasheet, quote on part number:ICS94241
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS94241
Programmable TCHTM for Differential PIIITM Processor
Recommended Application: VIA PL133-T style chipset with Intel differential PIII processor Output Features: · 2 - CPUs @2.5V · 13 - SDRAM @ 3.3V · 7 - PCI @3.3V, · 1 - 48MHz, @3.3V · 1 - 24MHz @ 3.3V · 2 - REF @3.3V, 14.318MHz. Features: · Programmable ouput frequency · Programmable ouput rise/fall time · Programmable output to output skew · Programmable spread spectrum for EMI control · Real time system reset output · Watchdog timer technology to reset system if over-clocking causes malfunction · Uses external 14.318MHz crystal Key Specifications: · CPU CPU: <175ps · SDRAM - SDRAM: <500ps · PCI PCI: <500ps · CPU-SDRAM: <500ps · CPU(early)-PCI: Min=1.0ns, Typ=2.0ns, Max=4.0ns
Pin Configuration
VDDREF GNDREF X1 X2 VDDPCI *FS4/PCICLK0 *FS3/PCICLK1 GNDPCI PCICLK2 PCICLK3 PCICLK4 PCICLK5 PCICLK6 VDDPCI BUFFER_IN GNDSDR SDRAM12 SDRAM11 VDDSDR SDRAM10 SDRAM9 GND48 SDATA SCLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 VTT_PWRGD# REF0 1 REF1/FS2** GNDCPU CPUCLK_CS CPUCLK0 VDDLCPU RESET# SDRAM0 GNDSDR SDRAM1 SDRAM2 VDDSDR SDRAM3 SDRAM4 GNDSDR SDRAM5 SDRAM6 VDDSDR SDRAM7 SDRAM8 AVDD48 48MHz/FS0** 24MHz/FS1**
48-Pin 300mil SSOP
* Internal Pull-up Resistor of 120K to VDD ** Internal Pull-down resistor of 120K to GND 1. This output has 1.5 to 2X drive strength
Block Diagram
Functionality
Bit2 Bi t7 Bit6 Bit5 Bit4 CP UCLK P CI CLK FS4 FS 3 FS 2 FS1 FS0 0 0 0 0 0 66. 67 33.33 0 0 0 0 1 66. 67 33.33 0 0 0 1 0 68. 67 34.33 0 0 0 1 1 71. 34 35.66 0 1 0 0 0 100.00 33.33 0 1 0 0 1 100.00 33.33 0 1 0 1 0 103.00 34.33 0 1 0 1 1 107.00 35.67 1 0 0 0 0 200.00 33.33 1 0 0 0 1 200.00 33.33 1 0 0 1 0 206.00 34.33 1 0 0 1 1 214.00 35.67 1 1 0 0 0 133.33 33.33 1 1 0 0 1 133.33 33.33 1 1 0 1 0 137.33 34.33 1 1 0 1 1 142.67 35.67 S pread Percentage +/- 0.25 Center Spread 0 to -0.5% Down Spread ± 0.25 Center Spread +/- 0.25 Center Spread +/- 0.25 Center Spread 0 to -0.5% Down Spread +/- 0.25 Center Spread +/- 0.25 Center Spread +/- 0.25 Center Spread 0 to -0.5% Down Spread +/- 0.25 Center Spread +/- 0.25 Center Spread +/- 0.25 Center Spread 0 to -0.5% Down Spread +/- 0.25 Center Spread +/- 0.25 Center Spread
For additional margin testing frequencies refer to pg 5 frequency table.
0453B--12/19/02
ICS94241
ICS94241
General Description
The ICS94241 is a single chip timing control hub for desktop designs using VIA PL133-T style chipset with Intel differential PIII processor. It provides all necessary clock signals for such a system. The ICS94241 is part of a whole new line of ICS clock generators and buffers called TCHTM (Timing Control Hub). ICS is the first to introduce a whole product line which offers full programmability and flexibility on a single clock device. This part incorporates ICS's newest clock technology which more robust features and functionality. Employing the use of a serially programmable I2C interface, this device can adjust the output clocks by configuring the frequency setting, the output divider ratios, selecting the ideal spread percentage, the output skew, the output strength, and enabling/disabling each individual output clock. TCH also incorporates ICS's Watchdog Timer technology in having a frequency reset feature to provide a safe setting under unstable system conditions.
Pin Configuration
PIN NUMBER 1, 5, 14, 19, 30, 36 2, 8, 16, 22, 33, 39, 45 3 4 6 PIN NAME VDD GND X1 X2 FS41,3 PCICLK0 FS31,3 7 13, 12, 11, 10, 9 15 17, 18, 20, 21, 28, 29, 31, 32, 34, 34, 35, 37, 38, 40 23 24 25 26 27 41 42 43 44 46 47 48 PCICLK1 PCICLK (6:2) BUFFER IN SDRAM (12:0) SDATA SCLK FS1
2,3
TYPE PWR PWR IN OUT IN OUT IN OUT OUT IN OUT I/O IN IN OUT OUT IN PWR OUT PWR OUT OUT IN OUT OUT IN
DESCRIPTION Power supply, nominal 3.3V Ground Cr ystal input, has inter nal load cap (36pF) and feedback resistor from X2 Cr ystal output, nominally 14.318MHz. Has inter nal load cap (36pF) Frequency select pin. Latched Input. Internal Pull-down to GND PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early) Frequency select pin. Latched Input. Internal Pull-down to GND PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early) PCI clock outputs. Synchronous to CPU clocks with 1-4ns skew (CPU early) Input to Fanout Buffers for SDRAM outputs. SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin (controlled by chipset) Data pin for I2C circuitr y 5V tolerant Clock pin of I2C circuitr y 5V tolerant Frequency select pin. Latched Input. 24MHz output clock 48MHz output clock Frequency select pin. Latched Input Analog power for 48MHz outputs Real time system reset signal for frequency ratio change or watchdog timmer timeout. This signal is active low. Supply for CPU clocks 2.5V nominal CPU clock outputs CPU clock output for chipset host clock Frequency select pin. Latched Input 14.318 MHz reference clock. 14.318 Mhz reference clock. This 3.3V LVTTL input is a level sensitive strobe used to determine when FS inputs are valid and are ready to be sampled (active low)
24MHz 48MHz FS02,3 AVDD48 RESET VDDLCPU CPUCLK0 CPUCLK_CS FS22,3 REF1 REF0 VTT_PWRGD#
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Internal Pull-down to GND on indicated inputs 3: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low.
0453B--12/19/02
2
ICS94241
General I2C serial interface information for the ICS94241 How to Write:
· · · · · · · · Controller (host) sends a start bit. Controller (host) sends the write address D2 (H) ICS clock will acknowledge Controller (host) sends a dummy command code ICS clock will acknowledge Controller (host) sends a dummy byte count ICS clock will acknowledge Controller (host) starts sending Byte 0 through Byte 20 (see Note) · ICS clock will acknowledge each byte one at a time · Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit. Controller (host) sends the read address D3 (H) ICS clock will acknowledge ICS clock will send the byte count Controller (host) acknowledges ICS clock sends Byte 0 through byte 8 (default) ICS clock sends Byte 0 through byte X (if X(H) was written to byte 8). · Controller (host) will need to acknowledge each byte · Controller (host) will send a stop bit · · · · · · ·
Ho w to Write:
Control l e r (Host) S t art Bit A ddres s D2(H ) Dum m y Command Code I CS (Slave/Receiver)
How to Read:
Controller (Host) Start Bit Address D3(H) ICS (Slave/Receiver)
A CK A CK
Dum m y Byte Count
ACK Byte Count
ACK
Byte 0
A CK
ACK
Byte 0
Byte 1
A CK
ACK
Byte 1
Byte 2
A CK
ACK
Byte 2
Byte 3
A CK
ACK
Byte 3
Byte 4
A CK
ACK
Byte 4
Byte 5
A CK
ACK
Byte 5
Byte 6
A CK
ACK If 7H has been written to B6 ACK
Byte 6
Byte 7
A CK
B y t e 18
A CK
B y t e 19
A CK
B y t e 20
A CK
S t op Bit
*See notes on the following page.
0453B--12/19/02
If 12H has been written to B6 ACK If 13H has been written to B6 ACK If 14H has been written to B6 ACK Stop Bit
Byte18 Byte 19 Byte 20
3
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