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Details, datasheet, quote on part number:ICS94258yG
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICS94258
Programmable System Clock Chip for PIII Processor
Recommended Application: ALI 1644 style chipset Output Features: · 2 - CPU clocks (including 1 free running) @ 2.5V · 13 - SDRAM @ 3.3V · 7 - PCI (including 1 free running and 1 early selectable free running) @ 3.3V · 2 - AGP @ 3.3V · 1 - IOAPIC 14.318MHz @ 2.5V · 1 - 48MHz, @ 3.3V · 1 - REF 14.318MHZ @ 3.3V, (selectable strength 1X or 2X) through I2C programming Features: · Programmable ouput frequency · Programmable ouput rise/fall time · Programmable CPU, SDRAM, PCI and AGP skew · Real time system reset output · Spread spectrum for EMI control typically by 7dB to 8dB, with programmable spread percentage · Watchdog timer technology to reset system if over-clocking causes malfunction · Uses external 14.318MHz crystal Skew Specifications: · CPU - CPU: <250ps · PCI - PCI: <500ps · SDRAM - SDRAM: <250ps · AGP - AGP: <500ps · PCI - AGP: <750ps · CPU - SDRAM:<350ps · CPU - PCI: <3ns
Pin Configuration
48-Pin 300mil SSOP & TSSOP
Notes: REF0 can be 1X or 2X strength controlled by I2C. * Internal Pull-up Resistor of 120K to VDD ** Internal Pull-down of 120K to GND 1. This input has 2X drive strength
Block Diagram
Functionality
FS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 FS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 FS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 CPU SDRAM 66.66 66.66 66.66 100.00 100.00 66.66 100.00 100.00 100.00 133.33 133.33 66.66 133.33 100.00 133.33 133.33 66.66 66.66 66.66 100.00 100.00 66.66 100.00 100.00 100.00 133.33 133.33 66.66 133.33 100.00 133.33 133.33
Note: PCICLK = 33.33MHz , AGP = 66.66MHz
94258 Rev B - 12/19/01 Third party brands and names are the property of their respective owners.
ICS94258
Pin Descriptions
PI N NUMBER 1 , 45 2 4 5 3, 11, 16, 23, 29, 34, 41, 48 6 , 8, 17, 21, 28, 35, 40 7 9 10 12 PI N N A M E VDDL I O A P IC X1 X2 GND VDD FS0 R EF
2, 3
T Y PE P WR OUT IN OUT P WR P WR IN OUT IN OUT OUT OUT IN OUT OUT OUT OUT IN OUT OUT
D E S C R I PT I O N P ow er supply pins, nominal 2.5V 2 . 5V clock outputs C r y s tal input,nominally 14.318M H z. C r y s tal output, nominally 14.318M H z. G ro u n d pins P ow er supply pins, nominal 3.3V F r eq uen cy select pin, 1X or 2X strength (default = 2X). 1 4 .3 1 8 M H z reference clock. F r eq uen cy select pin. A G P outputs defined as 2X PCI frequency. These may not be stopped. A G P outputs defined as 2X PCI frequency. These may not be stopped. F r ee running PCICLK not stoped by PCI_STOP# F r eq uen cy select pin. P C I clock output R eal time system reset signal for frequency value or watchdog timmer timeout. This signal is active low. Output is selectable via I C Byte 5 bit7 P C I clock outputs. P C I clock output. F un ctio n select pin, 1=Desktop M o d e, 0=M o b ile M o d e. F r ee running early PCI clock output (default) P C I clock output. A s y n ch r on o u s active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down w ill not be greater than 3ms. (See M O D E table for further information.) P C I clock output. This pin is active when M O D E = 0 (default) F r eq uen cy select pin. 4 8 M H z output clock. C lock input of I C input, 5V tolerant input A s y n ch r on o u s active low input pin used to power down the device into a low power state. The internal clocks are disabled and the VCO and the crystal are stopped. The latency of the power down w ill not be greater than 3ms. (See M O D E table for further information.) S D R A M clock output. This pin is active when M O D E = 1. T his asynchronous input halts CPU clock at logic "0" level when driven low, the stop selection can be programmed through I C . This is activated when M O D E = 0 (default) S D R A M clock output. This pin is active when M O D E = 1. S to p s all PCICLKs besides the PCICLK_F clocks at logic 0 level, w hen input low. This is activated when M O D E = 0 (default) S D R A M clock output. This pin is active when M O D E = 1. S elects EPCICLK _F This pin is active when M O D E = 0 (default). S D R A M clock output. This pin is active when M O D E = 1. S D R A M clock outputs. D ata pin for I C circuitry 5V tolerant F r ee running CPU clock. N ot affected by CPU_STO P # . 2 . 5V CPU clock.
2 2 2 2
FS1 AG P 0 AG P1 P C I C LK _ F FS2 PCICLK2
1, 3
2, 3
15
R ES ET# P C I C LK (1, 0) PCICLK3 MODE EPCICLK_F P C I C LK 4
1 1, 3
1 4 , 13 18 19
20
PD #
IN
P C I C LK 5 22 24 FS3 48M H z S CLK
2, 3
OUT IN OUT IN
25
PD #
1
IN
S D RA M 12 C P U _ S TO P # S D RA M 11 27 P C I_ S TO P # S D RA M 10 S E LP C I _ F SD RA M 9 S D R A M ( 8:0 ) S D A TA C P U C LK _ F C P U C LK
1 1
OUT IN OUT IN OUT IN OUT OUT I /O OUT OUT
26
30 3 1 , 32, 33, 36, 37, 38, 39, 42, 43 44 46 47
Notes: 1: Internal Pull-up Resistor of 120K to 3.3V on indicated inputs 2: Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to program logic Hi to VDD or GND for logic low. 3: Internal Pull-down resistor of 120K to GND on indicated inputs.
Third party brands and names are the property of their respective owners.
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ICS94258
General Description
The ICS94258 is a main clock synthesizer chip for PIII based systems with ALI 1644 style chipset. This provides all clocks required for such a system. The ICS94258 belongs to ICS new generation of programmable system clock generators. It employs serial programming I2C interface as a vehicle for changing output functions, changing output frequency, configuring output strength, configuring output to output skew, changing spread spectrum amount, changing group divider ratio and dis/enabling individual clocks. This device also has ICS propriety 'Watchdog Timer' technology which will reset the frequency to a safe setting if the system become unstable from over clocking.
Mode Pin - Power Management Input Control
MODE, Pin 18 (Latched Input) 0 1 Pin 20 PCICLK5 (Output) PD# (Input) Pin 25 PD# (Input) SDRAM12 (Output) Pin 26 CPU_STOP# (Input) SDRAM11 (Output) Pin 27 PCI_STOP# (Input) SDRAM10 (Output) Pin 30 SELPCI_F (Input) SDRAM9 (Output)
Third party brands and names are the property of their respective owners.
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