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Details, datasheet, quote on part number:ICSVF2509yG
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICSVF2509
3.3V Phase-Lock Loop Clock Driver
General Description
The ICSVF2509 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The ICSVF2509 operates at 3.3V VCC and drives up to nine clock loads. One bank of five outputs and one bank of four outputs provide nine low-skew, low-jitter copies of CLKIN. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLKIN. Each bank of outputs can be enabled or disabled separately via control (OEA and OEB) inputs. When the OE inputs are high, the outputs align in phase and frequency with CLKIN; when the OE inputs are low, the outputs are disabled to the logic low state. The ICSVF2509 does not require external RC filter components. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. The buffer mode shuts off the PLL and connects the input directly to the output buffer. This buffer mode, the ICSVF2509 can be use as low skew fanout clock buffer device. The ICSVF2509 comes in 24 pin 173mil Thin Shrink Small-Outline package (TSSOP) package.
Features
· · · · · · · ·
Meets or exceeds PC133 registered DIMM specification1.1 Spread Spectrum Clock Compatible Distributes one clock input to one bank of ten outputs Operating frequency 20MHz to 200MHz External feedback input (FBIN) terminal is used to synchrionize the outputs to the clock input No external RC network required Operates at 3.3V Vcc Plastic 24-pin 173mil TSSOP package
Block Diagram
FBOUT CLKA0 CLKA1 FBIN CLKIN PLL CLKA2 CLKA3 AVCC OEA CLKB0 CLKB1 CLKB2 CLKB3 OEB
0787B--06/10/03
Pin Configuration
AGND VCC CLKA0 CLKA1 CLKA2 GND GND CLKA3 CLKA4 VCC OEA FBOUT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLKIN AVCC VCC CLKB0 CLKB1 GND GND CLKB2 CLKB3 VCC OEB FBIN
CLKA4
24 Pin TSSOP 4.40 mm. Body, 0.65 mm. pitch
ICSVF2509
ICSVF2509
Pin Descriptions
P IN NUMBER 1 2, 10, 15 3 4 5 6, 7, 18, 19 8 9 11 12 13 14 16 17 20 21 22 23 24 PIN NAME AGND VCC CLKA0 CLKA1 CLKA2 GND CLKA3 CLKA4 OE A1 FBOUT FB I N OE B1 CLKB3 CLKB2 CLKB1 CLKB0 VCC AVCC CLKIN TY P E PWR PWR OUT OUT OUT PWR OUT OUT IN OUT IN IN OUT OUT OUT OUT PWR IN IN DE SCRIP TION Analog Ground Power Supply (3.3V) Buffered clock output, Bank A Buffered clock output, Bank A Buffered clock output, Bank A Ground Buffered clock output, Bank A Buffered clock output, Bank A Output enable (has internal pull_up). When high, normal operation. When low bank A clock outputs are disabled to a logic low state. Feedbac k output Feedbac k input Output enable (has internal pull_up). When high, normal operation. When low bank B clock outputs are disabled to a logic low state. Buffered clock output. Bank B Buffered clock output. Bank B Buffered clock output. Bank B Buffered clock output. Bank B Power Supply (3.3V) digital supply. Analog power supply (3.3V). When input is ground PLL is off and bypassed. Cloc k input
Note: 1. Weak pull-ups on these inputs
Functionality
INP UTS OE A 0 0 1 1 OEB 0 1 0 1 AVCC 3.33 3.33 3.33 3.33 CLKA (0:4) 0 0 Driv en Driv en OUTPUTS CLKB FBOUT (0:3) 0 Driv en Driv en Driv en 0 Driv en Driv en Driv en Source PLL PLL PLL PLL CLK IN CLK IN CLK IN CLK IN PLL Shutdown N N N N Y Y Y Y
Buffer Mode 0 0 0 0 0 Driv en 0 1 0 0 Driv en Driv en 1 0 0 Driv en 0 Driv en Driv en Driv en 1 1 0 Driv en Test mode: When AVCC is 0, shuts off the PLL and connects the input directly
0787B--06/10/03
to the output buffers
2
ICSVF2509
Absolute Maximum Ratings
Supply Voltage (AVCC) . . . . . . . . . . . . . . . . . Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . AVCC < (V cc + 0.7 V) 4.3 V GND 0.5 V to V cc + 0.5 V 0°C to +70°C 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - OUTPUT
TA = 0 - 70°C; VDD = V DDL = 3.3 V +/-10%; CL = 30 pF; RL = 500 Ohms (unless otherwise stated) PARAMETER SYMBOL CONDITIONS IOH = -8 mA Output High Voltage V OH Output Low Voltage V OL IOL = 8 mA VOH = 2.4 V Output High Current IOH VOH = 2.0 V VOL = 0.8 V Output Low Current IOL VOL = 0.55 V Ris e Time1 Tr VOL = 0.8 V, VOH = 2.0 V Fall Time1 Duty Cycle
1 1
MI N 2.4
TY P 2. 9 0.25 27 39 26 19 1.1 1.1 50
MA X UNITS V 0.4 V mA mA 2.1 2.7 52 75 100 100 ns ns % ps ps ps ps ns
0.5 0.5 48
Tf
VOH = 2.0 V, V OL = 0.8 V
Dt VT = 1.5 V;CL= 30 pF Cy c le to Cycle jitter TCYC - TCYC at 66-100 MHz ; loaded outputs Abs olute Jitter1 TJ ABS 10000 cycles; CL = 30 pF S kew1 Ts k VT = 1.5 V (Window) Output to Output Phas e error1 Delay Input-Output 1
1
Tp e DR1
VT = Vdd/2; CLKIN-FBIN VT = 1.5 V; PLL_EN = 0
-75 3.3
75 3.7
Guaranteed by design, not 100% tested in production.
0787B--06/10/03
3
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