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Details, datasheet, quote on part number:ICSVF2510yG-T
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Datasheet text preview:
Integrated Circuit Systems, Inc.
ICSVF2510
3.3V Phase-Lock Loop Clock Driver
General Description
The ICSVF2510 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the CLKIN signal with the CLKOUT signal. It is specifically designed for use with synchronous SDRAMs. The ICSVF2510 operates at 3.3V VCC and drives up to ten clock loads. One bank of ten outputs provide low-skew, low-jitter copies of CLKIN. Output signal duty cycles are adjusted to 50 percent, independent of the duty cycle at CLKIN. Outputs can be enabled or disabled via control (OE) inputs. When the OE inputs are high, the outputs align in phase and frequency with CLKIN; when the OE inputs are low, the outputs are disabled to the logic low state. The ICSVF2510 does not require external RC filter components. The loop filter for the PLL is included on-chip, minimizing component count, board space, and cost. The test mode shuts off the PLL and connects the input directly to the output buffer. This test mode, the ICSVF2510 can be use as low skew fanout clock buffer device. The ICSVF2510 comes in 24 pin 173mil Thin Shrink SmallOutline package (TSSOP) package.
Features
· · · · · · · ·
Meets or exceeds PC133 registered DIMM specification1.1 Spread Spectrum Clock Compatible Distributes one clock input to one bank of ten outputs Operating frequency 20MHz to 200MHz External feedback input (FBIN) terminal is used to synchrionize the outputs to the clock input No external RC network required Operates at 3.3V Vcc Plastic 24-pin 173mil TSSOP package
Block Diagram
FBOUT CLK0 CLK1 CLK2 FBIN CLKIN PLL CLK3 CLK4 AVCC CLK5 CLK6 CLK7 CLK8 CLK9 OE
Pin Configuration
AG ND VCC CLK0 CLK1 CLK2 G ND G ND CLK3 CLK4 VCC OE FBO UT 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 CLKIN AVCC VCC CLK9 CLK8 G ND G ND CLK7 CLK6 CLK5 VCC FBIN
24 Pin TSSOP 4.40 mm. Body, 0.65 mm. Pitch
0722A--05/07/03
ICSVF2510
ICSVF2510
Pin Descriptions
PIN # 1 2 , 10, 14 3 4 5 6, 7, 18, 19 8 9 11 12 13 15 16 17 20 21 22 23 24 PIN NAME AGND VCC CL K0 CL K1 CL K2 GND CL K3 CL K4 OE1 FBOUT FBIN CL K5 CL K6 CL K7 CL K8 CL K9 VCC AVCC CL KIN TYPE PWR PWR OUT OUT OUT PWR OUT OUT IN OUT IN OUT OUT OUT OUT OUT PWR IN IN DESC RIPTION Ana l o g Ground Pow er Supply (3.3V) Buffe red clock output. Buffe red clock output. Buffe red clock output. Gro un d Buffe red clock output. Buffe red clock output. Ou tp u t enable (has internal pull_up). When high, normal operation. When low, clock outputs are disabled to a logic low state. Fe e d ba ck output Fe e d ba ck input Buffe red clock output. Buffe red clock output. Buffe red clock output. Buffe red clock output. Buffe red clock output. Pow er Supply (3.3V) digital supply. Ana l o g power supply (3.3V). When input is ground PLL is off and bypassed. Cl ock input
Note: 1. Weak pull-ups on these inputs
Functionality
INPUTS OE 0 1 A VCC 3.33 3.33 CLK (9:0) 0 Driv en OUTPUTS FBOUT Driv en Driv en S ourc e PLL PLL P LL Shutdown N N Y Y
0 0 CLKIN 1 0 CLKIN Test mode: When AVCC is 0, shuts off the PLL and connects the input directly to the output buffers
Buffer Mode 0 Driv en Driv en Driv en
0722A--05/07/03
2
ICSVF2510
Absolute Maximum Ratings
Supply Voltage (AVCC) . . . . . . . . . . . . . . . . . Supply Voltage (VCC) . . . . . . . . . . . . . . . . . . Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . Ambient Operating Temperature . . . . . . . . . . Storage Temperature . . . . . . . . . . . . . . . . . . . AVCC < (V cc + 0.7 V) 4.3 V GND 0.5 V to V cc + 0.5 V 0°C to +70°C 65°C to +150°C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Electrical Characteristics - OUTPUT
TA = 0 - 70°C; VDD = V DDL = 3.3 V +/-10%; CL = 30 pF; RL = 500 Ohms (unless otherwise stated) PARAMETER SYMBOL CONDITIONS IOH = -8 mA Output High Voltage V OH Output Low Voltage V OL IOL = 8 mA VOH = 2.4 V Output High Current IOH VOH = 2.0 V VOL = 0.8 V Output Low Current IOL VOL = 0.55 V Ris e Time1 Tr VOL = 0.8 V, VOH = 2.0 V Fall Time1 Duty Cycle
1 1
MI N 2.4
TY P 2. 9 0.25 27 39 26 19 1.1 1.1 50
MA X UNITS V 0.4 V mA mA 2.1 2.7 52 75 100 100 ns ns % ps ps ps ps ns
0.5 0.5 48
Tf
VOH = 2.0 V, V OL = 0.8 V
Dt VT = 1.5 V;CL= 30 pF Cy c le to Cycle jitter TCYC - TCYC at 66-100 MHz ; loaded outputs Abs olute Jitter1 TJ ABS 10000 cycles; CL = 30 pF S kew1 Ts k VT = 1.5 V (Window) Output to Output Phas e error1 Delay Input-Output 1
1
Tp e DR1
VT = Vdd/2; CLKIN-FBIN VT = 1.5 V; PLL_EN = 0
-75 3.3
75 3.7
Guaranteed by design, not 100% tested in production.
0722A--05/07/03
3
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