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Part: M2004-12
Category:
Timing Circuits
-> Frequency Translation
Description: Frequencytranslation PLL
Company: Integrated Circuit System
Datasheet: Download M2004-12 datasheet File size : 58 kB
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Datasheet text preview:
Integrated Circuit Systems, Inc.
Preliminary Information
M2006-12
VCSO BASED FEC CLOCK PLL WITH APS
PIN ASSIGNMENT (9 x 9 mm SMT)
FIN_SEL1 GND APC DIF_REF0 nDIF_REF0 REF_SEL DIF_REF1 nDIF_REF1 VCC FIN_SEL0 FEC_SEL0 FEC_SEL1 FEC_SEL2 FEC_SEL3 VCC DNC DNC DNC 27 26 25 24 23 22 21 20 19
GENERAL DESCRIPTION
The M2006-12 is a VCSO (Voltage Controlled SAW Oscillator) based clock generator PLL designed for clock frequency translation and jitter attenuation. The device supports both forward and inverse FEC (Forward Error Correction) clock multiplication ratios. Multiplication ratios are pin-selected from pre-programming look-up tables.
FEATURES
Similar to the M2006-02 (and pin-compatible), but with an automatic protection switch (APS) function APS engages when a 4 ns or greater clock phase change is detected at the phase detector, such as might occur when reselecting reference clocks APS helps to ensure MTIE compliance by lowering loop bandwidth during the phase realignment APS is not recommended for complex FEC ratio translation when using an unstable reference; the M2006-02 is recommended for these applications In addition to the APS circuit, the APC (automatic phase compensation) pin enables absorption of the input phase change. Supports input reference and VCSO frequencies up to 700MHz, supports loop timing modes Single 3.3V power supply Small 9 x 9 mm SMT (surface mount) package
28 29 30 31 32 33 34 35 36
M2006-12
(Top View)
18 17 16 15 14 13 12 11 10
P0_SEL P1_SEL nFOUT0 FOUT0 GND nFOUT1 FOUT1 VCC GND
Figure 1: Pin Assignment
Example I/O Clock Frequency Combinations Using M2006-12-622.0800 and Inverse FEC Ratios
FEC PLL Ratio Mfec / Rfec 1/1 239/255 238/255 237/255 236/255 Base Input Rate 1 (MHz) 622.0800 663.7255 666.5143 669.3266 672.1627 Output Clock (either output) MHz 622.08 or 155.52
Table 1: Example I/O Clock Frequency Combinations
Note 1: Input reference clock can be the base frequency shown divided by "Mfin" (as shown in Table 3 on pg. 3).
SIMPLIFIED BLOCK DIAGRAM
M2006-12
APC DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL 4 2 Mfec / Rfec Divider LUT Mfin Divider LUT P0_SEL
Figure 2: Simplified Block Diagram
0 Rfec Div 1 Mfec Div Mfin Div VCSO P0 Div
GND GND GND OP_IN nOP_OUT nV C VC OP_OUT nOP_IN
1 2 3 4 5 6 7 8 9
FOUT0 nFOUT0
FEC_SEL3:0 FIN_SEL1:0
P1 Div
FOUT1 nFOUT1
P1_SEL
M2006-12 Datasheet Rev 0.6
M2006-12 VCSO Based FEC Clock PLL with APS
Revised 10Mar2003
Integrated Circuit Systems, Inc.
Communications Modules
w w w. i c s t . c o m
tel (508) 852-5400
Integrated Circuit Systems, Inc.
M2006-12
VCSO BASED FEC CLOCK PLL WITH APS
Preliminary Information
DETAILED BLOCK DIAGRAM
RLOOP CLOOP RPOST CPOST CPOST RLOOP CLOOP OP_OUT RPOST nOP_OUT nV C VC
External Loop Filter Components
M2006-12
APC DIF_REF0 nDIF_REF0 DIF_REF1 nDIF_REF1 REF_SEL
MUX Phase Detector
OP_IN
nOP_IN
RIN
0
Rfec Divider
RIN Loop Filter Amplifier
1
Phase Locked Loop (PLL)
SAW Delay Line
Phase Shifter
VCSO
Mfec Divider
Mfin Divider P0 Divider FOUT0 nFOUT0
FEC_SEL3:0
4
Mfec / Rfec Divider LUT Mfin Divider LUT
P = 1 ( P0_SEL = 0 ) or 4 ( P0_SEL = 1 )
FIN_SEL1:0
2
P1 Divider
P = 1 ( P1_SEL = 0 ) or 4 ( P1_SEL = 1 )
FOUT1 nFOUT1
P0_SEL
P1_SEL
Figure 3: Detailed Block Diagram
PIN DESCRIPTIONS
Number 1, 2, 3, 10, 14, 26 4 9 5 8 6 7 11, 19, 33 12, 13 15, 16 17 18 20 21 22 23 24 25 27 28 29 30 31 32 34, 35, 36 Name GND OP_IN nOP_IN nOP_OUT OP_OUT nVC VC VCC FOUT1, nFOUT1 FOUT0, nFOUT0 P1_SEL P0_SEL nDIF_REF1 DIF_REF1 REF_SEL nDIF_REF0 DIF_REF0 APC FIN_SEL1 FIN_SEL0 FEC_SEL0 FEC_SEL1 FEC_SEL2 FEC_SEL3 DNC I/O Configuration Description
Ground Input Output Input Power O utput Input Input Input Input Input Input No internal terminator Internal pull-down resistor1 Internal pull-down resistor1 Internal pull-down resistor1 Internal pull-down resistor1 Internal pull-down resistor1 Internal pull-down resistor1 Internal pull-up resistor1
Power supply ground connections.
External loop filter connections. See Figure 4.
Power supply connection, connect to +3.3V. Clock output pairs. Differential LVPECL. P Divider controls. LVCMOS/LVTTL. (For P0_SEL, P1_SEL, see Table 5 on pg. 3. Reference clock input pair 1. Differential LVPECL or LVDS. Reference clock input selection. LVCMOS/LVTTL: Logic 1 selects DIF_REF1, nDIF_REF1. Logic 0 selects DIF_REF0, nDIF_REF0. Reference clock input pair 0. Differential LVPECL or LVDS. Automatic Phase Compensation. LVCMOS/LVTTL: Logic 1 - Device absorbs input phase transients. Logic 0 - Device doesn't absorb transients. Input clock frequency selection. LVCMOS/LVTTL. (For FIN_SEL1:0, see Table 3 on pg. 3. FEC PLL divider ratio selection. LVCMOS/ LVTTL. (For FEC_SEL3:0, see Table 4 on pg. 3.) Do Not Connect.
Table 2: Pin Descriptions
Input
Note 1: For typical values of internal pull-down and pull-up resistors, see DC Characteristics (Pull-down and Pull-up) on pg. 7.
M2006-12 Datasheet Rev 0.6 Integrated Circuit Systems, Inc.
2 of 8 Communications Modules
Revised 10Mar2003 w w w. i c s t . c o m
tel (508) 852-5400
Integrated Circuit Systems, Inc.
M2006-12
VCSO BASED FEC CLOCK PLL WITH APS
Preliminary Information Post-PLL Dividers The M2006-12 also features two post-PLL dividers, one for each output pair. The "P1" divider is for FOUT1 and nFOUT1; the "P0" divider is for FOUT0 and nFOUT0. Each divides the VCSO frequency to produce one of two output frequencies (1/4 or 1/1 of the VCSO frequency). The P1_SEL and P0_SEL pins each select the value for their corresponding divider.
P1_SEL, P0_SEL
PLL DIVIDER LOOK-UP TABLES
Mfin (Frequency Input) Divider Look-Up Table (LUT) The FIN_SEL1:0 pins select the feedback divider value ("Mfin").
FIN_SEL1:0
Mfin Value 1 4 8 32
1 1 0 0
1 0 1 0
Sample Ref. Freq. (MHz) 1 622.08 2 155.52 77.76 19.44
M2006-12-622.0800
P Value 4 1
Table 3: Mfin (Frequency Input) Divider Look-Up Table (LUT)
Note 1: Example with M2006-12-622.0800 and "Non-FEC ratio" selection made from Table 4 (FEC_SEL2=1). Note 2: Do not use with FEC_SEL3:0=1100 or 1101.
1 0
Output Frequency (MHz) 155.52 622.08
M2006-12-622.0800
Table 5: P Divider Selector, Values, and Frequencies
FUNCTIONAL DESCRIPTION
FEC PLL Ratio Dividers Look-up Table (LUT) The FEC_SEL3:0 pins select the FEC feedback and reference divider values Mfec and Rfec.
FEC_SEL3:0 Mfec Rfec
The M2006-12 is a PLL (Phase Locked Loop) based clock generator that generates output clocks synchronized to one of two selectable input reference clocks. An internal high "Q" SAW filter provides low jitter signal performance and controls the output frequency of the VCSO (Voltage Controlled SAW Oscillator). Configurable FEC feedback and reference dividers (the "Mfec Divider" and "Rfec Divider") provide the multiplication ratios necessary to accomodate clock translation for both forward and inverse Forward Error Correction. In addition, a configurable feedback divider (labeled "Mfin Divider") provides the broader division options needed to accomodate various reference clock frequencies. For example, the M2006-12-622.0800 (see "Ordering Information" on pg. 8) has a 622.08MHz VCSO frequency:
Description
0 0 0 0
0 0 0 0
0 0 1 1
0 1 0 1
236 79 14 239 236 79 14 239 255 85 15 255 1 2 4 8
255 85 15 255 236 79 14 239 236 79 14 239 1 2 4 8
0100 0101 0110 0 1 1 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0
1101 1110 1111
Inverse FEC ratio Inverse FEC ratio, equivalent to 237/255 Inverse FEC ratio, equivalent to 238/255 Inverse FEC ratio Non-FEC ratio, complement to 000 1 Non-FEC ratio, complement to 001 1 Non-FEC ratio, complement to 010 1 Non-FEC ratio, complement to 011 1 FEC ratio FEC ratio, equivalent to 255/237 FEC ratio, equivalent to 255/238 FEC ratio Non-FEC ratio. Do not use when FIN_SEL1:0=11. The maximum phase detector frequency is 175MHz 2 Non-FEC ratio
2
· The inverse FEC PLL ratios (at top of Table 4) enable
the M2006-12-622.0800 to accept "base" input reference frequencies of: 663.7255, 666.5143, 669.3266, 672.1627, and 622.08MHz. The Mfin feedback divider enables the actual input reference clock to be the "base" input frequency divided by 1, 4, 8, or 32. Therefore, for the base input frequency of 622.08MHz, the actual input reference clock frequencies can be: 622.08, 155.52, 77.76, and 19.44MHz. (See Table 3 on pg. 3.)
Table 4: FEC PLL Ratio Dividers Look-up Table (LUT)
·
Note 1: The complementary "Inverse FEC ratio" and "Non-FEC ratio" selections use the same Mfec Divider ratio. This results in the same PLL loop bandwidth and damping factor for both selections, enabling them to be actively switched in a given application. See "Maintaining PLL Lock:" on pg. 4. Note 2: The various "Non-FEC ratio" settings can be used to actively change PLL loop bandwidth in a given application.
M2006-12 Datasheet Rev 0.6 Integrated Circuit Systems, Inc.
3 of 8 Communications Modules
Revised 10Mar2003 w w w. i c s t . c o m
tel (508) 852-5400
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