Details, datasheet, quote on part number: SSTL16857C
CategoryTiming Circuits => Clock Buffers => Latch (Register)
TitleLatch (Register)
CompanyIntegrated Circuit System
DatasheetDownload SSTL16857C datasheet


Features, Applications

Recommended Applications: DDR Memory Modules Provides complete DDR DIMM logic solution with ICS95V857 SSTL_2 compatible data registers Product Features: Differential clock signal Meets SSTL_2 signal data Supports SSTL_2 class & II specifications Low-voltage operation - VDD 2.7V 48 pin TSSOP package


Notes: H = High Signal Level L = Low Signal Level = Transition LOW-to-HIGH = Transition HIGH -to LOW X = Irrelevant Output level before the indicated steady state input conditions were established.

6.10 mm. Body, 0.50 mm. pitch = TSSOP 4.40 mm. Body, 0.40 mm. pitch = TSSOP (TVSOP)

The is a universal bus driver designed for to 2.7V VDD operation and SSTL_2 I/O levels, except for the LVCMOS RESET# input. Data flow from Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV16857C supports low-power standby operation. A logic level "Low" at RESET# assures that all internal registers and outputs (Q) are reset to the logic "Low" state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET# must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic "Low" level during power up. In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#. Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state, the register will be cleared and the outputs will be driven to a logic "Low" level quickly relative to the time to disable the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power standby state, the register will become active quickly relative to the time to enable the differential input receivers. When the data inputs are at a logic level "Low" and the clock is stable during the "Low"-to-"High" transition of RESET# until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic "Low" level.

Storage Temperature. Supply Voltage. Input Voltage 1. Output Voltage 1,2. Input Clamp Current. Output Clamp Current. Continuous Output Current. VDD, VDDQ or GND Current/Pin. -0.5 to VDD -0.5 to VDDQ ±100 mA Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V0 >VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51.

Package Thermal Impedance 3. 55°C/W Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.


DESCRIPTION Supply Voltage I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage Input High Voltage Level RESET# Input Low Voltage Level Common mode Input Range CLK, CLK# Differential Input Voltage Cross Point Voltage of Differential Clock Pair High-Level Output Current Low-Level Output Current Operating Free-Air Temperature


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