|Category||Timing Circuits => Clock Buffers => Latch (Register)|
|Company||Integrated Circuit System|
|Datasheet||Download SSTL16859C datasheet
Recommended Applications: DDR Memory Modules Provides complete DDR DIMM logic solution with ICS95V857 SSTL_2 compatible data registers Product Features: Differential clock signals Meets SSTL_2 signal data Supports SSTL_2 class II specifications on outputs Low-voltage operation - VDD to 2.7V Available in 64 pin TSSOP and 56 pin VFQFN (MLF2) packages
Q10A Q9A VDDQ GND Q3A Q2A GND Q1A Q13B VDDQ Q7B Q6B GND VDDQ Q2B Q1B VDDQ GND D13 D12 VDD VDDQ GND D10 D9 GND D8 D7 RESET# GND CLK# CLK VDDQ VDD VREF D6 GND D4 D3 GND VDDQ VDD D2 D1 GND VDDQInputs RESET# CLK X or Floating or H CLK# X or Floating X or Floating Outputs Q0(2)
Notes: H = "High" Signal Level L = "Low" Signal Level = Transition "Low"-to-"High" = Transition "High"-to-"Low" X = Don't Care Output level before the indicated steady state input conditions were established.
The is a universal bus driver designed for to 2.7V VDD operation and SSTL_2 I/O levels, except for the LVCMOS RESET# input. Data flow from Q is controlled by the differential clock (CLK/CLK#) and a control signal (RESET#). The positive edge of CLK is used to trigger the data flow and CLK# is used to maintain sufficient noise margins where as RESET#, an LVCMOS asynchronous signal, is intended for use at the time of power-up only. ICSSSTV16859C supports lowpower standby operation. A logic level "Low" at RESET# assures that all internal registers and outputs (Q) are reset to the logic "Low" state, and all input receivers, data (D) and clock (CLK/CLK#) are switched off. Please note that RESET# must always be supported with LVCMOS levels at a valid logic state because VREF may not be stable during power-up. To ensure that outputs are at a defined logic state before a stable clock has been supplied, RESET# must be held at a logic "Low" level during power up. In the DDR DIMM application, RESET# is specified to be completely asynchronous with respect to CLK and CLK#. Therefore, no timing relationship can be guaranteed between the two signals. When entering a low-power standby state, the register will be cleared and the outputs will be driven to a logic "Low" level quickly relative to the time to disable the differential input receivers. This ensures there are no glitches on the output. However, when coming out of low-power standby state, the register will become active quickly relative to the time to enable the differential input receivers. When the data inputs are at a logic level "Low" and the clock is stable during the "Low"-to-"High" transition of RESET# until the input receivers are fully enabled, the design ensures that the outputs will remain at a logic "Low" level.
PIN NUMBER PIN NAME Q (13:1) GND VDDQ D (13:1) CLK CLK# VDD RESET# VREF TYPE OUTPUT PWR INPUT PWR INPUT Data output Ground Output supply voltage, 2.5V nominal Data input Positive master clock input Negative master clock input Core supply voltage, 2.5V nominal Reset (active low) Input reference voltage, 2.5V nominal DESCRIPTION
PIN NUMBER PIN NAME Q (13:1) GND VDDQ D (13:1) CLK CLK# VDD RESET# VREF Center PAD TYPE OUTPUT PWR INPUT PWR INPUT PWR Data output Ground Output supply voltage, 2.5V nominal Data input Positive master clock input Negative master clock input Core supply voltage, 2.5V nominal Reset (active low) Input reference voltage, 2.5V nominal Ground (MLF2 package only) DESCRIPTION
Storage Temperature. Supply Voltage. Input Voltage1. Output Voltage1,2. Input Clamp Current. Output Clamp Current. Continuous Output Current. VDD, VDDQ or GND Current/Pin. Package Thermal Impedance 3
Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V0 >VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.PARAMETER DD V DDQ VREF VTT VI VIH (DC) VIH (AC) VIL (DC) VIL (DC) VIH VIL VICR VID VIX IOH IOL TA
DESCRIPTION Supply Voltage I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage Input High Voltage Level RESET# Input Low Voltage Level Common mode Input Range CLK, CLK# Differential Input Voltage Cross Point Voltage of Differential Clock Pair High-Level Output Current Low-Level Output Current Operating Free-Air Temperature
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