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Part: EI16C550
Category:
Communication
-> UARTs
Description: Universal Asynchronous Receiver Transmitter (UART)
Company: IMP, Inc.
Datasheet: Download EI16C550 datasheet File size : 74 kB
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Datasheet text preview:
Ei16C550 FIFO UART
Semiconductor, Inc.
FEATURES
ï ï ï ï 5V Operation Full duplex asynchronous receiver and transmitter Easily interfaces to most popular microprocessors Adds or deletes standard asynchronous communication bits (start, stop, and parity) to or from a serial data stream Independently controlled transmitter, receiver, line status, and data set interrupts Programmable baud rate generator allows division of any input clock by 1 to (216-1) and generates the internal 16 x clock Independent receiver clock input MODEM control functions (CTS, RTS, DSR, DTR, RI,and DCD) Fully programmable serial interface characteristics: - 5, 6, 7, or 8 bit characters - Even, odd, or no-parity bit generation and detection - 1, 1.5, or 2 stop bit generation - Baud generation (DC to 56k baud) False start bit detection Complete status reporting capabilities
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Tri-StateÆTTL drive capabilities for bidirectional data bus and control bus Line break generation and detection Internal diagnostic capabilities: - Loopback controls for communications link fault isolation - Break, parity overrun, and framing error simulation
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Fully prioritized interrupt systems controls 16 byte FIFO for reduced CPU overhead
DESCRIPTION
The Epic Ei16C550 Universal Asynchronous Receiver Transmitter (UART) is a CMOS-VLSI communication device in a single package. The UART performs serial to parallel conversion on data characters received from a peripheral device or a MODEM, and parallel-to-serial conversions on data characters received from the CPU. The CPU can read the complete status of the UART at any time during the functional operation. Status information reported includes the type and condition of the transfer operation being performed by the UART, as well as any error conditions (party, overrun, framing, or break detect).
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Part Numbers May Be Marked With "IMP" or "Ei."
PIN CONFIGURATION
DSR ï
CTS ï 38
VCC
CD ï
N.C.
D4 D3 D2 D1 D0 NC VCC RIï DCDï DSRï CTSï
XTAL1 XTAL2 DOSTRï DOSTR VSS NC DISTRï DISTR DDIS TXRDYï ADSï
XTAL1
XTAL2
-IOW
GND
N.C.
IOW
IOR
IOR ï
N.C.
DDIS ï
40-PIN DIP
44-PIN PLCC
48-PIN TQFP
7 For additional information, contact IMP, Inc. at 408.432.9100 or visit www.impweb.com
IMP, Inc. acquired Epic products on January 26, 2001. (see press release at http://www.impweb.com/PRESS/PR012601.htm)
TXRDY ï
AS
D0 D1 D2 D3 D4 D5 D6 D7 RCLK SIN SOUT CS0 CS1 CS2ï BAUDOUTï XTAL1 XTAL2 DOSTRï VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
E i 1 6 C 5 5 0
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VCC RIï DCDï DSRï CTSï MR OUT1ï DTRï RTSï OUT2ï INTRPT RXRDYï A0 A1 A2 ADSï TXRDYï DDIS DISTR DISTRï
48
47
46
45
44
43
42
41
40
39
6 5 4 3 2 1 44 43 42 41 40
37 36 35 34 33 32
N.C.
RI ï
D4
D3
D2
D1
D0
N.C.
1 2 3 4 5 6 7 8 9 10 11 12 14 13 15 16 17 18 19 20 21 22 23 24
N.C. RESET OP1 ï DTR ï RTS ï OP2 ï INT RXRDY ï A0 A1 A2 N.C.
18 19 20 21 22 23 24 25 26 27 28
D5 D6 D7 RCLK SIN NC SOUT CS0 CS1 CS2ï BAUDOUTï
7 8 9 10 11 12 13 14 15 16 17
Ei16C550
39 38 37 36 35 34 33 32 31 30 29
MR OUT1ï DTRï RTSï OUT2ï NC INTRPT RXRDYï A0 A1 A2
D5 D6 D7 RCLK N.C. RX TX CS0 CS1 CS2 ï BAUDOUT ï
Ei16C550
31 30 29 28 27 26 25
Ei16C550 FIFO UART
Semiconductor, Inc.
The UART includes a programmable baud generator which is capable of dividing the timing reference clock input by divisors of 1 to (216-1), and producing a 16 x clock to drive the receiver logic. Also included in the
UART is a complete MODEM control capability, and processor interrupt system that may be software tailored to the users requirement to minimize the computing needed to handle the communications link.
BLOCK DIAGRAM
INTERNAL
DATA BUS D7-D0 (1-8) DATA BUS BUFFER
RECEIVER BUFFER REGISTER LINE CONTROL REGISTER DIVISOR LATCH (LS) DIVISOR LATCH (MS BAUD GENERATOR
RECEIVER SHIFT REGISTER
(10)
SIN
A0 A1 A2 CS0 CS1 CS2· ADR MR DISTR DISTR· DOSTR DOSTR· DDIS TXRDY· XTAL1 XTAL2 RXRDY·
(28) (27) (26) (12) (13) (14) (25) (35) (22) (21) (19) (18) (23) (24) (16) (17) (29)
RECEIVER TIMING & CONTROL (15)
(9)
RCLK
BAUDOUT
SELECT AND CONTROL LOGIC
LINE STATUS REGISTER FIFO MODEM CONTROL REGISTER MODEM STATUS REGISTER INTERRUPT ENABLE REGISTER INTERRUPT ID REGISTER FIFO CONTROL REGISTER
TRANSMITTER TIMING & CONTROL
TRANSMITTER SHIFT REGISTER
(11)
SOUT
(32) (36) (33) (37) (38) (39) (34) (31)
RT S · CTS· DTR· DSR· DCD· · RI OUT1· OUT2·
POWER SUPPLY
(40) (20)
3.3, 5V GND
INTERRUPT CONTROL LOGIC
MODEM CONTROL LOGIC
(30)
INTRPT
8
Others parts begin by ei
EI-1
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