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Part: IMP5241IMP5241
Category:
Interface and Interconnect
-> SCSI
-> SCSI Terminator
Description: 24 Tssop 36 Ssop 9-Line Multimode Lvd/se Scsi Terminator
Company: IMP, Inc.
Datasheet: Download IMP5241IMP5241 datasheet File size : 29 kB
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Datasheet text preview:
1 I M P 5 2 41 / 4 2 / 4 3
DATA COMMUNIC ATIONS
9-Line Multimode LVD/SE SCSI Terminator
The IMP5241/42/43 is a multimode SCSI terminator that conforms to the SCSI Parallel Interconnect-2 (SPI-2) specification developed by the T10 standards committee for low voltage differential (LVD) termination, while providing backwards compatibility to the SCSI, SCSI-2, and SPI single-ended specifications. Multimode compatibility permits the use of legacy devices on the bus without hardware alterations. Automatic mode selection is achieved through voltage detection on the diffsense line. The IMP5241/42/43 delivers the ultimate in SCSI bus performance while saving component cost and board area. Elimination of the external capacitors also mitigates the need for a lengthy capacitor selection process. The individual high bandwidth drivers also maximize channel separation and reduce channel to channel noise and cross talk. The high bandwidth architecture insures ULTRA2 performance while providing a clear migration path to ULTRA3 and beyond. When the IMP5241/42/43 is enabled, the differential sense (DIFFSENSE) pin supplies a voltage between 1.2V and 1.4V. In application, this pin is tied to the DIFFSENSE input of the corresponding LVD transceivers. This action enables the LVD transceiver function. DIFFSENSE is capable of supplying a maximum of 15mA. Tying the DIFFSENSE pin HIGH places the IMP5241/42/43 in a high impedance state indicating the presence of an HVD device. Tying the pin LOW places the part in a single-ended mode while also signaling the multimode transceiver to operate in a single-ended mode. Recognizing the needs of portable and configurable peripherals, the IMP5241/42/43 have a TTL compatible sleep/disable mode. During this
Key Features
N N N N N N N N N N N N Auto-selectable LVD or single-ended termination 3.0pF maximum disabled output capacitance Fast response, no external capacitors required Compatible with active negation drivers 15µA supply current in disconnect mode Logic command disconnects all termination lines DIFFSENSE line driver Ground driver integrated for single-ended operation Current limit and thermal protection Hot-swap compatible (single-ended) Compatible with SCSI 1, 2, 3, FAST-20, and the pending SPI-2 LVD Pin compatible with DS2118, UCC5630 and LX5241/42/43
sleep/disable mode, power dissipation is reduced to a meager 15µA while also placing all outputs in a high impedance state. Also during sleep/disable mode, the DIFFSENSE function is disabled and is placed in a high impedance state. Another key feature of the IMP5241/42/43 is the master/slave function. Driving this pin HIGH or floating the pin enables the 1.3V DIFFSENSE reference. Driving the pin LOW disables the on board DIFFSENSE reference and enables use of an external master reference device.
Block Diagram
VTERM DISCONNECT (IMP5241) DISCONNECT (IMP5242) LVD 1.25V M/S 10mA 1.07mA Window Comp. 20k DIFF B Power ON MODE Control & Delay SE HVD LVD Power ON & MODE Delay
5241/42_01.eps
SE 2.85V, 22.5mA Internal VREF 1.30V Power ON SE 2.2V 1.07mA 200 52.5 52.5 20 SE DISC/HVD LVD
1 of 9
LVD(-) / SE SE HVD LVD LVD(+) / SE (Pseudo-GND)
Latch SE HVD LVD
DIFFSENSE
© 2001 IMP, Inc.
Data Communications
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1 I M P 5 2 41 / 4 2 / 4 3
Pin Configuration
S S O P- 3 6
NC NC NC 1+ 1 2+ 2 HEATSINK HEATSINK 1 2 3 4 5 6 7 8 9 IMP5241/42 36 VTERM 35 HVD 34 LVD 33 SE 32 9 31 9+ 30 8 29 8+ 28 HEATSINK 27 HEATSINK 26 HEATSINK 25 7 24 7+ 23 6 22 6+ 21 DIFF B 20 DIFFSENSE 19 MASTER/SLAVE DB Package
5241/42_02.eps
T S S O P- 2 8
NC 1+ 1 2+ 2 NC 3+ 3 4+ 1 2 3 4 5 6 7 8 9 IMP5243 28 VTERM 27 NC 26 9 25 9+ 24 8 23 8+ 22 NC 21 7 20 7+ 19 6 18 6+ 17 DIFF B 16 DIFFSENSE 15 MASTER/SLAVE
5243_02.eps
T S S O P- 2 4
1+ 1 2+ 2 3+ 3 4+ 4 5+ 1 2 3 4 5 6 7 8 9 IMP5241/42 24 VTERM 23 NC 22 9 21 9+ 20 8 19 8+ 18 7 17 7+ 16 6 15 6+ 14 DIFFSENSE 13 MASTER/SLAVE DW Package
5241/42_03.eps
HEATSINK 10 3+ 11 3 12 4+ 13 4 14 5+ 15 5 16 DISCONNECT 17 GND 18
4 10 5+ 11 5 12 DISCONNECT 13 GND 14
5 10 DISCONNECT 11 GND 12
Ordering Information
Part Number
IMP5241CDB IMP5242CDB IMP5241CPW IMP5242CPW IMP5243CPW
Temperature Range
0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C 0°C to 70°C
Package
36-pin Plastic SSOP 36-pin Plastic SSOP 24-pin Plastic TSSOP 24-pin Plastic TSSOP 28-pin Plastic TSSOP
5241/42_t02.eps
Note:
For Tape and Reel, append the letter "T" to part number. (i.e. IMP5241CDBT)
Absolute Maximum Ratings1
TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . +7V Operating Junction Temperature Plastic (DB, PW Packages) . . . . . . . . . . . . . 150°C Storage Temperature Range . . . . . . . . . . . . . . 65°C to 150°C Lead Temperature (Soldering, 10 sec.) . . . . . . 300°C Note: 1. Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal.
Thermal Data
DB Package: Thermal Resistance Junction-to-Ambient, JA . . . . . . 50°C/W PW Package: Thermal Resistance Junction-to-Ambient, JA . . . . . . 100°C/W 2 Junction Temperature Calculation: TJ = TA + (PD x JA). The JA numbers are guidelines for the thermal performance of the device/pc-board system. No ambient airflow is assumed.
408-432-9100/www.impweb.com
© 2001 IMP, Inc.
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1 I M P 5 2 41 / 4 2 / 4 3
Pin Description
Pin Name
1-, 2-, 3-, 4-, 5-, 6-, 7-, 8-, 9VTERM
Function
Negative signal termination lines for LVD mode. Signal termination lines for SE mode. Power supply pin for terminator. Connect to SCSI bus TermPwr. Must be decoupled by one 4.7µF low-ESR capacitor for every three terminator devices. It is absolutely necessary to connect this pin to the decoupling capacitor through a very low impedance (big traces on PCB). Keeping distances very short from the decoupling capacitors to the VTERM pin is also critical. The value of the decoupling capacitor is somewhat layout dependant and some applications may benefit from an additional 0.1µF decoupling capacitor at the VTERM pin. Enables / disables terminator. See Table 2 for logic levels. Terminator ground pin. Connect to ground. Sometimes referred to as M/S pin. Used to select which terminator is the controlling device. MASTER/SLAVE pin HIGH or Open enables the DIFFSENSE output drive. See Table 1. This is a dual function pin. It drives the SCSI bus DIFFSENS line. It is also the sense pin to detect the SCSI bus mode (LVD, SE or HVD). DIFFSENSE output drive can be disabled with a LOW level on the MASTER/SLAVE pin. See Table 1 and Table 2. Internally connected to DIFF B pin through 20k resistor. Internally connected to DIFFSENSE pin through 20k resistor. It can be used as a mode sense pin when the device is a non-controlling terminator (MASTER/SLAVE pin is LOW). An RC filter (20k / 0.1µF) is not required on the IMP5241/42, as it has an internal timer. Single-ended output. When HIGH, the terminator is operating in SE mode. Low Voltage Differential output. When HIGH, the terminator is operating in LVD mode. High Voltage Differential output. When HIGH, the terminator is operating in HVD mode. Attached to die mounting pad, but not bonded to GND pin. Pins should be considered a heat sink only, and not a true ground connection. It is recommeneded that these pins be connected to ground, but can be left floating.
5241/42_t08.at3
1+, 2+, 3+, 4+, 5+, 6+, 7+, 8+, 9+ Positive signal termination lines for LVD mode. Pseudo-ground lines for SE mode.
DISCONNECT (IMP5241) DISCONNECT (IMP5242) GND MASTER / SLAVE DIFFSENSE
DIFF B
SE LVD HVD HEATSINK
© 2001 IMP, Inc.
Data Communications
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