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Details, datasheet, quote on part number:HYB18RL25616AC-5
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Datasheet text preview:
HYB18RL25632AC HYB18RL25616AC
Graphics & Speciality DRAMs
256 Mbit DDR Reduced Latency DRAM
Version 1.42 Nov. 2002
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM
Edition Jun. 2002 This edition was realized using the software system FrameMakerâ. Published by Infineon Technologies, Marketing-Kommunikation, Balanstraße 73, 81541 München © Infineon Technologies 6/30/2002. All Rights Reserved. Attention please! As far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. The information describes the type of component and shall not be considered as assured characteristics. Terms of delivery and rights to change design reserved. For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or the Infineon Technologies Companies and Representatives worldwide (see address list). Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies is an approved CECC manufacturer. Packing Please use the recycling operators known to you. We can also help you get in touch with your nearest sales office. By agreement we will take packing material back, if it is sorted. You must bear the costs of transport. For packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. Components used in life-support devices or systems must be expressly authorized for such purpose! Critical components1 of Infineon Technologies, may only be used in life-support devices or systems 2 with the express written approval of Infineon Technologies. 1 A critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that lifesupport device or system, or to affect its safety or effectiveness of that device or system. 2 Life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. If they fail, it is reasonable to assume that the health of the user may be endangered.
HYB18RL25616/32AC Revision History: Current Version 1.42 Subjects (major changes since last revision) Previous Version: 1.34 New formating of the specification document 16 17 23 25, 26 35 Previous Version: 1.4 15 Previous Version: 1.41 22, 23 22 23 22,23 22 23 tDQSQ changed back to tQSQ (typo) Data Window = min(tDQSH, tDQSL) - 2 * tQSQmax Note 4 : tQSQ and tQSQHZ are absolute values Power up sequence modified: Addresses may be applied with specified setup and hold timings during MRS commands. Elimination of 4mA Driver Strength in MRS Elimination of Configurations 5 and 6 in Configuration Table. tCKDQS (max) changed to 3.7ns for all speed sorts tCKDQS (min) changed from 2.3ns to 2.7ns for all speed sorts Introduction of "Read followed by Write, Write data on bus prior to Read data" timings. Reference Voltage range changed to 0.49 * VDDQ to 0.51 * VDDQ AC Operation : HSTL strong : VIH and VIL changed to Vref +/- 0.3V
Version 1.42
P age 2
Infineon Technologies
This specification is preliminary and subject to change without notice
HYB18RL25616/32AC 256 Mbit DDR Reduced Latency DRAM 1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
1.1 1.2 1.3 1.3.1 1.4 1.5 1.5.1 1.5.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 Ball Configuration Package and Ballout . . . . . . . . . . . . . . . . . . . . . . .6 Ball Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Command Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 Description of Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Clocks, Commands and Addresses . . . . . . . . . . . . . . . . . . . . . . . . .15 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Mode Register Set Command (MRS) . . . . . . . . . . . . . . . . . . . . . . . .17 Configuration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Writes (WR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Write - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 Write - Cyclic Bank Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 Write Data Mask Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 Write followed by Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Reads (RD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Read - Basic Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Read - Cyclic Bank Access . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Burst Length (BL) = 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Burst Length (BL) = 4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Read followed by Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 Test Access Port (TAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Test Clock (TCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Test Mode Select (TMS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Test Data-In (TDI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Test Data-Out (TDO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 TAP Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Instruction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Bypass Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Boundary Scan Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Identification (ID) Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 TAP Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Boundary Scan Exit Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 x16 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 x32 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .32 TAP Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 JTAG TAP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 JTAG TAP Controller State Diagram . . . . . . . . . . . . . . . . . . . . . . . . .34 JTAG DC Operating Conditons . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 JTAG AC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 JTAG AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . .35 JTAG Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35
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Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 2.2 2.3 2.4 2.5 2.5.1 2.5.2 2.5.2.1 2.5.2.2 2.5.3 2.5.3.1 2.5.3.2 2.5.4 2.5.4.1 2.5.4.2 2.6 2.6.1 2.6.2 2.6.2.1 2.6.2.2 2.6.3
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IEEE 1149.1 Serial Boundary Scan (JTAG) . . . . . . . . . . . . . . 29
3.1 3.1.1 3.1.2 3.1.3 3.1.4 3.2 3.2.1 3.2.2 3.2.3 3.2.4 3.3 3.4 3.4.1 3.4.2 3.5 3.6 3.7 3.8 3.9 3.10 3.11
Version 1.42
P age 3
Infineon Technologies
This specification is preliminary and subject to change without notice
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