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Details, datasheet, quote on part number: HYB39S256800
 
 
Part numberHYB39S256800
Category
Description
CompanyInfineon Technologies Corporation
DatasheetDownload HYB39S256800 datasheet
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Specifications, Features, Applications

Multiple Burst Read with Single Write Operation Automatic Command and Controlled Precharge

Data Mask for Read / Write control (x4, x8) Data Mask for byte control (x16) Auto Refresh (CBR) and Self Refresh Power Down and Clock Suspend Mode 8192 refresh cycles ms (7,8 s) Random Column Address every CLK ( 1-N Rule) Single 3.3V 0.3V Power Supply LVTTL Interface versions Plastic Packages: P-TSOPII-54 400mil width x16) -7.5 parts for PC133 3-3-3 operation -8 parts for PC100 2-2-2 operation -8A parts for PC100 3-2-2 operation

Fully Synchronous to Positive Clock Edge 70 C operating temperature Four Banks controlled & BA1 Programmable CAS Latency: & 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: Full page burst length (optional) for sequential wrap around

The HYB39S256400/800/160CT(L) are four bank Synchronous DRAM's organized as 4 banks x4, 4 banks 8MBit x8 and 4 banks 4Mbit x16 respectively. These synchronous devices achieve high speed data transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock. The chip is fabricated with INFINEON's advanced m 256MBit DRAM process technology. The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length, CAS latency and speed grade of the device. Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3V 0.3V power supply and are available in TSOPII packages.

x 4 SDRAM x 4 SDRAM x 4 SDRAM x 8 SDRAM x 8 SDRAM x 8 SDRAM x 16 SDRAM x 16 SDRAM x 16 SDRAM Low Power Versions (on request)

CLK CKE CS RAS CAS BA0, BA1 Clock Input Clock Enable Chip Select Row Address Strobe Column Address Strobe Write Enable Address Inputs Bank Select DQ DQM, LDQM, UDQM Vdd Vss Vddq Vssq NC Data Input /Output Data Mask Power (+3.3V) Ground Power for DQ's 3.3V) Ground for DQ 's not connected





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