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Details, datasheet, quote on part number:HYB5118165BST-50
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Datasheet text preview:
1M × 16-Bit Dynamic RAM 1k Refresh (Hyper Page Mode-EDO)
Advanced Information · 1 048 576 words by 16-bit organization · 0 to 70 °C operating temperature · Hyper Page Mode-EDO-operation · Performance: -50 -60 60 15 30
HYB 5118165BSJ/BST-50/-60 HYB 3118165BSJ/BST-50/-60
tRAC RAS access time tCAC CAS access time tAA tRC
Access time from address Read/Write cycle time
50 13 25 84 20
ns ns ns ns ns
104 25
tHPC Hyper page mode (EDO) cycle time
· Power Dissipation, Refresh & Addressing: HYB5118165 -50 Power Supply Addressing Refresh Active TTL Standby CMOS Standby 715 11 5.5 10/10 632 -60 5 V ± 10 %
HYB3118165 -50 10/10 468 7.2 3.6 414 mW mW mW -60 3.3 V ± 0.3 V
1024 cycles / 16 ms
· Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh and hidden refresh · All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible · Plastic Package: P-SOJ-42-1 400 mil P-TSOPII-50/44-1 400 mil
Semiconductor Group
1
1998-10-01
HYB 5118165BSJ/BST-50/-60 HYB 3118165BSJ/BST-50/-60 1M × 16 EDO-DRAM
The HYB 5(3)118165 are 16 MBit dynamic RAMs based on die revisions "G" & "F" and organized as 1 048 576 words by 16-bits. The HYB 5(3)118165 utilizes a submicron CMOS silicon gate process technology, as well as advanced circuit techniques to provide wide operating margins, both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)18165 to be packaged in a standard SOJ-42 and TSOPII-50/44 plastic package with 400 mil width. These packages provide high system bit densities and are compatible with commonly used automatic testing and insertion equipment. Ordering Information Type HYB 5118165BSJ-50 HYB 5118165BSJ-60 HYB 3118165BSJ-50 HYB 3118165BSJ-60 Ordering Code Package Q67100-Q1107 Q67100-Q1108 on request on request P-SOJ-42-1 400 mil P-SOJ-42-1 400 mil P-SOJ-42-1 400 mil P-SOJ-42-1 400 mil P-TSOPII-50/44-1 400 mil P-TSOPII-50/44-1 400 mil P-TSOPII-50/44-1 400 mil P-TSOPII-50/44-1 400 mil Descriptions 5V 5V 50 ns EDO-DRAM 60 ns EDO-DRAM
3.3 V 50 ns EDO-DRAM 3.3 V 60 ns EDO-DRAM 5V 5V 50 ns EDO-DRAM 60 ns EDO-DRAM
HYB 5118165BST-50 on request HYB 5118165BST-60 on request HYB 3118165BST-50 on request HYB 3118165BST-60 on request
3.3 V 50 ns EDO-DRAM 3.3 V 60 ns EDO-DRAM
Semiconductor Group
2
1998-10-01
HYB 5118165BSJ/BST-50/-60 HYB 3118165BSJ/BST-50/-60 1M × 16 EDO-DRAM
Pin Names and Configuration HYB 5(3)118165 Row Address Inputs Column Address Inputs Row Address Strobe Upper Column Address Strobe Lower Column Address Strobe Output Enable Data Input/Output Read/Write Input Power Supply Ground (0 V) Not Connected A0 - A9 A0 - A9 RAS UCAS LCAS OE I/O1 - I/O16 WE
VCC VSS
N.C.
P-SOJ-42-1 (400 mil)
V CC I/O1 I/O2 I/O3 I/O4 V CC I/O5 I/O6 I/O7 I/O8 N.C. N.C. WE RAS N.C. N.C. A0 A1 A2 A3 V CC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 42 V SS 41 I/O16 40 I/O15 39 I/O14 38 I/O13 37 V SS 36 I/O12 35 I/O11 34 I/O10 33 I/O9 32 N.C. 31 LCAS 30 UCAS 29 OE 28 A9 27 A8 26 A7 25 A6 24 A5 23 A4 22 V SS
SPP02812
P-TSOPII-50/44-1 (400 mil)
VCC I/O1 I/O2 I/O3 I/O4 VCC I/O5 I/O6 I/O7 I/O8 N.C.
1 2 3 4 5 6 7 8 9 10 11 50 49 48 47 46 45 44 43 42 41 40
VSS I/O16 I/O15 I/O14 I/O13 VSS I/O12 I/O11 I/O10 I/O9 N.C.
N.C. N.C. WE RAS A11 / N.C. A10 / N.C. A0 A1 A2 A3 VCC
15 16 17 18 19 20 21 22 23 24 25
36 35 34 33 32 31 30 29 28 27 26
SPP03457
N.C. LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
Semiconductor Group
3
1998-10-01
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