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Details, datasheet, quote on part number:HYS72V32301GR-7.5
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Datasheet text preview:
HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules 3.3 V 168-pin Registered SDRAM Modules PC133 128 MByte Module PC133 256 MByte module PC133 512 MByte Module PC133 1 GByte Module PC133 2 GByte Module
· 168-pin Registered 8 B yte Dual-In-Line SDRAM Module for PC and Server main memory applications · One bank 16M × 72, 32M x 72, 64M × 72and 128M x 72, two bank 128M × 72 and 256M x 72 organization · Optimized for ECC applications with very low input capacitances · JEDEC standard Synchronous DRAMs (SDRAM) Programmable CAS Latency, Burst Length and Wrap Sequence (Sequential & Interleave) · Single + 3.3 V (± 0.3 V) power supply · Auto Refresh (CBR) and Self Refresh · Performance: speed grade
fCK tCK tAC fCK tCK tAC Clock Frequency (max.) @ CL = 3 Clock Cycle Time (min.) @ CL = 3 Clock Access Time (min.) @ CL= 3 Clock Frequency (max.) @ CL = 2 Clock Cycle Time (min.) @ CL = 2 Clock Access Time (min.) @ CL= 2
· Pr ogrammable CAS Latency, Burst Length, and Wrap Sequence (Sequential & Interleave) · All inputs and outputs are LVTTL compatible · Serial Presence Detect with E2P ROM · Utilizes SDRAMs in TSOPII-54 packages with registers and PLL. · Card Size: 133.35 mm × 38.10 / 43.18 mm with Gold contact pads (JEDEC MO-161) · These modules all fully compatible with the current industry standard PC133 and PC100 specifications
-7
133 7.5 5.4 133 7.5 5.4
-7.5
133 7.5 5.4 100 10 6
Unit
MHz ns ns MHz ns ns
Description
The HYS 7 2Vxx3xxGR-7 and -7.5 are industry standard 168-pin 8-byte Dual in-line Memory Modules (DIMMs) orga nized as 16M × 7 2, 32M x 72, 64M × 72, 128M × 72 and 256M x 72 high speed memory arrays designed with Synchronou s DRAMs (SDRAMs) for ECC applications. All control and address signals are registered on-DIMM an d the design incorporates a PLL circuit for the Clock inputs. Use of an on-board register reduces capacitive loading on the input signals but are delayed by one cycle in arriving at the SDRAM devices. Decoupling capacitors are mounted on the PC board. The DIMMs use a serial presence detects scheme implemented via a serial E2PROM using the 2-pin I2C protocol. The first 128 b yte s are utilized by the DIMM manufacturer and the second 12 8 bytes are available to the end user. All Infineon 168-pin DIMMs provide a high performance, flexible 8-byte interface in a 133.35 mm long footprint.
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HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules
Ordering Information Type PC133-333:
HYS 72V16300 GR-7.5 -C HYS 72V16300 GR-7.5 -E HYS 72V16301GR-7.5-C2 HYS 72V32301GR-7.5-C2 HYS 72V32300GR-7.5-C2 HYS 72V32300GR-7.5-D HYS 72V64300 GR-7.5 -C2 HYS 72V64300 GR-7.5 -D PC133R-333 -54 2-B2 one bank 128 MB Reg. DIMM PC133R-333 -54 2-B2 one bank 128 MB Reg. DIMM PC133R-333 -54 2-B2 one bank 256 MB Reg. DIMM PC133R-333 -54 2-AA one bank 256 MB Reg. DIMM PC133R-333 -54 2-B2 one bank 512 MB Reg. DIMM 6 4 MBit (x4) 1 28 MBit (x8) 1 28 Mbit (x4) 2 56 Mbit (x8) 2 56 MBit (x4) 2 56 MBit(x4, stacked) 5 12 MBit (x4) 5 12 MBit(x4, stacked)
Compliance Code
Description
S DRAM Technology
HYS 72V12832 0GR -7. 5-C2 PC133R-333 -54 2-B2 two banks 1 GByte Reg. DIMM HYS 72V12832 0GR -7. 5-D HYS 72V12830 0GR -7. 5-A HYS 72V25632 0GR -7. 5-A PC133R-333 -54 2-B2 one bank 1 GByte Reg. DIMM PC133R-333 -54 2-B2 two banks 2 GByte Reg. DIMM
PC133-222:
HYS 72V16300 GR-7-E HYS 72V16301GR-7-C2 HYS 72V32301GR-7-C2 HYS 72V32300GR-7-D HYS 72V64300 GR-7-D HYS 72V12832 0GR -7-D HYS 72V12830 0GR -7-A HYS 72V25632 0GR -7-A PC133R-222 -54 2-B2 one bank 128 MB Reg. DIMM PC133R-222 -54 2-B2 one bank 128 MB Reg. DIMM PC133R-222 -54 2-B2 one bank 256 MB Reg. DIMM PC133R-222 -54 2-AA one bank 256 MB Reg. DIMM PC133R-222 -54 2-B2 one bank 512 MB Reg. DIMM PC133R-222 -54 2-B2 two banks 1 GByte Reg. DIMM PC133R-222 -54 2-B2 one bank 1 GByte Reg. DIMM PC133R-222 -54 2-B2 two banks 2 GByte Reg. DIMM 6 4 MBit (x4) 1 28 MBit (x8) 1 28 Mbit (x4) 2 56 Mbit (x8) 2 56 MBit (x4) 2 56 MBit (x4, stacked) 5 12 MBit (x4) 5 12 MBit (x4, stacked)
Note: All part numbers end with a place code (not shown), designating the die revision. Consult factory for
current revision. Example: HYS 64V3 2300GR-7.5-D, indicating Rev.D dies are used for SDRAM comp onents.
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HYS 72Vxx3xxGR PC133 Registered SDRAM-Modules
Pin Definitions and Functions
A0 - A11, A12 BA0, BA1 DQ0 - DQ63 Address Inputs (A12 is used for 256Mbit based modules only) Bank Selects Da ta Input/Output DQMB0 - DQMB7 CS0 - CS3 REGE*) Data Mask Chip Select Regist er Enable "H" or N.C = registered mode "L" = buffered mode Po wer (+ 3 .3 V) Gro und Clock for Presence Detect Se rial Data Out No Connection
CB0 - CB7 RAS CAS WE CKE0 CLK0 - CLK3
Ch eck Bits Ro w Address Strobe Co lumn Address Strobe Re ad/Write Input Clock Enable Clock Input
VDD VSS SC L SD A N.C.
Note: To confirm to this specification, motherboards must pull this pin to high state or no connect Address Format Density Organization Memory SDRAMs Banks 128 MB 16M × 72 128 MB 16M × 72 256 MB 32M x 72 256 MB 32M x 72 512 MB 64M × 72 1 GB 1 GB 2 GB 128M × 72 128M × 72 256M × 72 1 1 1 1 1 2 1 2 16M × 4 16M x 8 32M x 4 32M x 8 64M × 4 64M × 4 # of # of row/bank/ Refresh Period Interval SD RAMs columns bits 18 9 18 9 18 36 12/2/10 12/2/10 12/2/11 13/2/10 13/2/11 13/2/11 13/2/12 13/2/12 4k 4k 4k 8k 8k 8k 8k 8k 64 ms 15.6 µs 64 ms 15.6 µs 64 ms 15.6 µs 64 ms 7.8 µs 64 ms 7.8 µs 64 ms 7.8 µs 64ms 64ms 7.8 µs 7.8 µs
128M × 4 18 128M × 4 36
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