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Part: PEB1761

Category:
 Communication
   -> Network
     -> Ethernet/DS1/E1 (T1/E1)
       -> Framers/Mappers

Description: Metro Mapper 2 .5 G Multi-service Framer For Sts-48 / Stm- 16 , STS - 12 / ST M-4

Company: Infineon Technologies Corporation

Datasheet: Download PEB1761 datasheet     File size : 263 kB

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Preliminary
Product Brief
MetroMapperTM 2.5G
Multi-Service Framer for STS-48/ STM-16, STS-12/STM-4
T h e MetroMapperTM 2.5G is a multi-service framer capable of mapping datacom traffic into SONET/SDH transport payloads. On the line side, the MetroMapperTM 2.5G supports protected STS-48/STM-16 and STS-12/ STM-4 interfaces. On the client side, one OIF SPI-3 with up to 128 logical channels are provided. Data from the SPI-3 interface is encapsulated by either the GFP-F, LAPS (X.85/.86) or PPP mapping scheme. Low-order and high-order virtual concatenation (VCAT) with Link Capacity Adjustment Schemes (LCAS) for up to 128 virtual concatenated channels is supported. MetroMapperTM 2.5G provides Ethernet VLAN ID processing and enables MPLS label update processing.
Applications
A c c e s s / edge aggregation MSPP S w i t c h e s and Routers
Features
Framer M u l t i - R a t e SONET/SDH framer with STS/AU and VT/TU pointer processing capabilities P r o c e s s e s a single STS-48/STM-16 or a quad STS-12/STM-4, STS-3/STM-1 P a y l o a d Pointer interpretation and generation P r o v i d e s full performance monitoring for high- and low-order paths P r o v i d e s high-order and low-order virtual concatenation according to ITU-T G.707 S u p p o r t s up to 128 virtual concatenated groups (VCG) F l e x i b l e concatenation of up to 48 high-order paths and up to 64 low-order paths into any virtual concatenation group S u p p o r t s up to 1344 VT1.5/TU-11 or 1008 VT2/TU-12 low-order paths P r o v i d e s following mapping schemes: ­ A U - 4 / VC-4 / TUG-3 ­ A U - 4 / VC-4 / TUG-3 / TUG-2 ­ A U - 3 / VC-3 or STS-1 / STS-SPE E x t e r n a l buffer for up to 64 m s differential delay compensation D i f f e r e n t VCG group types are defined: ­ N × VC-12, N × VC-11, N × VT1.5 SPE, N × VT2 SPE (N 64) ­ N × VC-3, N × STS1 SPE (N 48) ­ N × VC-4, N × STS3c SPE (N 16) F u l l y integrated support for the Link Capacity Adjustment Scheme (LCAS) protocol according to ITU-T G. 7042
S u p p o r t s 1+1 line protection T O H / P O H add/drop interface F u l l y SONET/SDH compliant E n c a ps u l a t i o n / D e c a ps u l a t i o n P r o v i d e s GFP-F mapping according to T1X1.5/ ITU-T G. 7041 P P P processing according to IETF RFC 1662 L A P S processing according to ITU-T X.85 + X.86 1 2 8 logical channels, can be independently configured P P P protocol support: MPLS Unicast & IP Version 4/6 L A P S protocol support: Ethernet and IP Version 4/6 G F P Client management frame insertion/detection S P I - 3 Interface 1 2 8 logical channels running in 32 bit mode P a c k e t mode with variable block length I n t e r l e a v e d channel mode Ethernet E n a b l e s Ethernet via VLAN tagging ­ V L A N update including tag, retag and change of VLAN IDs ­ p e r f o r m s 512-4096 entry (port, VLAN) lookup ­ s u p p o r t s VLAN double tagging Diagnostics Va r i o u s loop back modes for system debugging implemented Interfaces S o u r c e synchronous STS-48/STM-16 or quad STS-12/STM-4 interfaces for working and protected links operating at 622 MHz LVDS or 78 MHz LVTTL T O H / P O H add/drop interface O I F compliant SPI-3 interface M e m o r y Interface including two DDR-SRAM and optionally 1 ZBT SRAM interface for L2 update function 6 6 MHz CPU interface I E E E 1149.1 JTAG boundary scan interface D o c u m e n ta t i o n D a t a Sheet H a r d w a r e Evaluation System W I N E A S Y Software for MS Windows with graphical user interface
w w w. i n f i n eo n . c o m / wi r e l i n e
Optical Networking
Never
stop
thinking.
Preliminary
Product Brief
Block Diagram
M emo r y I n ter face
T OH / POH A D D Interface
VL A N Pr o cessi n g SPI -3 M PL S label Pr o cessi n g
GFP -F P PP X . 8 5/ 8 6
Data Assemb., M apping, TU P ointer
Data Assemb., M apping, AU P ointer
P ointer Gen.
Frame Gen.
S TM 16/ S TS 48 4x S TM 4/ S TS 12 W&P 622M / 155M
Tx System Packet
T x Layer 2 Pr o cessi n g
T x Packet Pr o ces.
T x LO POH VC A T LCAS
T x HO POH VC A T LCAS
Tx POH
Tx Tx TT OH OH
L in e Interface Single STM-16/ STS-48 Quad STM-4 / STS-12
T x Line T x Line
SPI -3 VL A N Pr o cessi n g M PL S label Pr o cessi n g Rx System Packet R x Layer 2 Pr o cessi n g
GFP -F P PP X . 8 5/ 8 6
P ointer P r oc. P OH Ter min. Delay Calcul.
P ointer P r oc. P OH Ter min. Delay Calcul.
DeFr amer
S TM 16/ S TS 48 4x S TM 4/ S TS 12 W&P
R x Packet Pr o ces.
R x LO VC A T / LCAS
R x HO VC A T / LCAS
Rx Rx T OH T OH
Rx Rx Lne Liine
32-b i t u P Interface
M emo r y I/F
T OH / POH D R OP Interface
Product Summary
Ty p e S a l e s Code Package 1 0 2 0 FineLine BGA (33 × 33 mm) M e t r o M a p p e r TM 2.5G P E B 1 7 6 1
Application Example
Ethernet/MPLS Switching Ethernet MAC QoS ; L2 VPN Service Rate Adaptation VPLS MAC VPN / PWE-3 VLAN/MPLS Processing Services GFP Mapping VCAT / LCAS Working & Protect SDH/ SONET
FE/GE
Multi-MAC Bridge
SPI-3
Ethernet/MPLS Switch
SPI-3
MetroMapper 2.5G
VCAT-LCAS Framer&Mapper
Single STM-16 / STS-48 Quad STM-4 / STS-12
TDM Switch
L2 / L3 Processing Traffic Management Switching
FE/GE Aggregation
NP / TM Switch
SPI-3
MetroMapper 2.5G
VCAT-LCAS Framer&Mapper
Single STM-16 / STS-48 Quad STM-4 / STS-12
TDM Switch
Ethernet MAC Rate Adaptation VLAN/MPLS Processing
FE /GE
Multi-MAC Bridge
SPI-3
MetroMapper 2.5G
VCAT-LCAS Framer&Mapper
Single STM-16 / STS-48 Quad STM-4 / STS-12
TDM Switch
How to reach us: h t t p : / / w w w. i n f i n e o n . c o m P u b l i s h e d by I n f i n e o n Technologies AG, S t . - M a r t i n - S t r a s s e 53, 8 1 6 6 9 München © Infineon Technologies AG 2004. All Rights Reserved. Template: pb_tmplt.fm/4
A t t e n t i o n please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office.
Wa r n i n g s Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in lifesupport devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Ordering No. B115-H8436-X-X-7600 Printed in Germany PS 0604.5 R&L
P u b l i s h e d by Infineon Technologies AG


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