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Details, datasheet, quote on part number:W27L010S-90
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Datasheet text preview:
Preliminary W27L010 128K × 8 ELECTRICALLY ERASABLE EPROM
GENERAL DESCRIPTION
The W27L010 is a high speed, low power consumption Electrically Erasable and Programmable Read Only Memory organized as 131072 × 8 bits. It requires only one supply in the range of 3.0V to 3.6V in normal read mode. The W27L010 provides an electrical chip erase function.
FEATURES
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High speed access time: 90/120 nS (max.) Read operating current: 10 mA (max.) Erase/Programming operating current: 30 mA (max.) Standby current: 20 µA (max.) Low voltage power supply range, 3.0V to 3.6V
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+14V erase/+12V programming voltage Fully static operation All inputs and outputs directly TTL/CMOS compatible Three-state outputs Available packages: 32-pin 600 mil DIP, 450 mil SOP and PLCC
PIN CONFIGURATIONS
Vpp A16 A15 A12 A7 A6 A5 A4 A3 A2 A1 A0 Q0 Q1 Q2 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-pin DIP 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 / VVP pcGN p c MC 1 33 21 Vcc PGM NC A14 A13 A8 A9 A11 OE A10 CE Q7 Q6 Q5 Q4 Q3
BLOCK DIAGRAM
PGM CE OE
CONTROL
OUTPUT BUFFER
Q0 . . Q7
A0 .
DECODER
. A16
CORE ARRAY
VCC GND VPP
PIN DESCRIPTION
SYMBOL A0-A16 Q0-Q7
A14 A13 A8 A9 A11 OE A10 CE Q7
AAA 111 256
A7 A6 A5 A4 A3 A2 A1 A0 Q0
4 5 6 7 8 9 10 11 12 1 13 4
3 0 29 28 27 26 32-pin PLCC 25 24 23 1 1 1 1 1 2 22 5 6 7 8 9 0 21
32
Q QGQ QQQ 1 2N3 456 D
CE OE PGM VPP VCC GND NC
DESCRIPTION Address Inputs Data Inputs/Outputs Chip Enable Output Enable Program Enable Program/Erase Supply Voltage Power Supply Ground No Connection
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Publication Release Date: February 1999 Revision A1
Preliminary W27L010
FUNCTIONAL DESCRIPTION
Read Mode
Like conventional UVEPROMs, the W27L010 has two control functions, both of which produce data at the outputs. CE is for power control and chip select. OE controls the output buffer to gate data to the output pins. When addresses are stable, the address access time (TACC) is equal to the delay from CE to output (TCE), and data are available at the outputs TOE after the falling edge of OE, if TACC and TCE timings are met.
Erase Mode
The erase operation is the only way to change data from "0" to "1." Unlike conventional UVEPROMs, which use ultraviolet light to erase the contents of the entire chip (a procedure that requires up to half an hour), the W27L010 uses electrical erasure. Generally, the chip can be erased within 100 mS by using an EPROM writer with a special erase algorithm. Erase mode is entered when VPP is raised to VPE (14V), VCC = VCE (5V), CE low, OE high, A9 = VHH (14V), A0 low, and all other address pins low and data input pins high. Pulsing PGM low starts the erase operation.
Erase Verify Mode
After an erase operation, all of the bytes in the chip must be verified to check whether they have been successfully erased to "1" or not. The erase verify mode automatically ensures a substantial erase margin. This mode will be entered after the erase operation if VPP = VPE (14V), CE low, and OE low, PGM high.
Program Mode
Programming is performed exactly as it is in conventional UVEPROMs, and programming is the only way to change cell data from "1" to "0." The program mode is entered when VPP is raised to VPP (12V), VCC = VCP (5V), CE low , OE hig, the address pins equal the desired addresses, and the input pins equal the desired inputs. Pulsing PGM low starts the programming operation.
Program Verify Mode
All of the bytes in the chip must be verified to check whether they have been successfully programmed with the desired data or not. Hence, after each byte is programmed, a program verify operation should be performed. The program verify mode automatically ensures a substantial program margin. This mode will be entered after the program operation if VPP = VPP (12V), CE low, OE low, and PGM high.
Erase/Program Inhibit
Erase or program inhibit mode allows parallel erasing or programming of multiple chips with different data. When CE high , erasing or programming of non-target chips is inhibited, so that except for the CE , the W27L010 may have common inputs.
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Preliminary W27L010
Standby Mode
The standby mode significantly reduces VCC current. This mode is entered when CE high. In standby mode, all outputs are in a high impedance state, independent of OE and PGM.
Two-line Output Control
Since EPROMs are often used in large memory arrays, the W27L010 provides two control inputs for multiple memory connections. Two-line control provides for lowest possible memory power dissipation and ensures that data bus contention will not occur.
System Considerations
EPROM power switching characteristics require careful device decoupling. System designers are concerned with three supply current issues: standby current levels (Isb), active current levels (Icc), and transient current peaks produced by the falling and rising edges of CE . Transient current magnitudes depend on the device output's capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 µF ceramic capacitor connected between its Vcc and GND. This high frequency, low inherentinductance capacitor should be placed as close as possible to the device. Additionally, for every eight devices, a 4.7 µF electrolytic capacitor should be placed at the array's power supply connection between Vcc and GND. The bulk capacitor will overcome voltage slumps caused by PC board trace inductances.
TABLE OF OPERATING MODES
VCC = 3.3V, VPP = 12V, VPE = 14V, VHH = 12V, VCP = 5V, X=VIH or VIL
MODE CE Read Output Disable Standby (TTL) Standby (CMOS) Program Program Verify Program Inhibit Erase Erase Verify Erase Inhibit Product IdentifierManufacturer Product Identifier-device VIL VIL VIH VCC ±0.3V VIL VIL VIH VIL VIL VIH VIL VIL OE VIL VIH X X VIH VIL X VIH VIL X VIL VIL
PINS
PGM X
X X X VIL VIH X VIL VIH X X X
A0 X X X X X X X VIL X X VIL VIH
A9 X X X X X X X VPE X X VHH VHH
VCC VCC VCC VCC VCC VCP VCP VCP VCP VCP VCP VCC VCC
VPP VCC VCC VCC VCC VPP VPP VPP VPE VPE VPE VCC VCC
OUTPUTS DOUT High Z High Z High Z DIN DOUT High Z FF (Hex) DOUT High Z DA (Hex) 01 (Hex)
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Publication Release Date: February 1999 Revision A1
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