|
Details, datasheet, quote on part number:PEEL22CV10AZTI-25
| |
Datasheet text preview:
Commercial/ Industrial
PEELTM 22CV10AZ -25 CMOS Programmable Electrically Erasable Logic Device
Features
s s
Ultra Low Power Operation - VCC = 5 Volts ±10% - Icc = 10 µA (typical) at standby - Icc = 2 mA (typical) at 1 MHz - tPD = 25ns. CMOS Electrically Erasable Technology - Superior factory testing - Reprogrammable in plastic package - Reduces retrofit and development costs Development/Programmer Support - Third party software and programmers - ICT PLACE Development Software and PDS-3 programmer
s
Architectural Flexibility - 133 product terms x 44 input AND array - Up to 22 inputs and 10 I/O pins - 12 possible macrocell configurations - Synchronous preset, asynchronous clear - Independent output enables - Programmable clock source and polarity - 24-pin DIP/SOIC/TSSOP and 28-pin PLCC Application Versatility - Replaces random logic - Pin and JEDEC compatible with 22V10 - Ideal for power-sensitive systems
s
s
General Description
The PEELTM22CV10AZ is a Programmable Electrically Erasable Logic (PEELTM) device that provides a low power alter native to ordinary PLDs. The PEELTM22CV10AZ is available in 24-pin DIP SOIC, TSSOP and 28-pin PLCC , packages (see Figure 19). A "zero-power" (100µA max. ICC) standby mode makes the PEELTM22CV10AZ ideal for power sensitive applications such as handheld meters, portable communication equipment and laptop computers/ peripherals. EE-reprogrammability provides the convenience of instant reprogramming for development and a reusable production inventory minimizing the impact of programming changes or errors. EEreprogrammability also improves factory testability, thus ensuring the highest quality possible. The PEELTM22CV10AZ is JEDEC file compatible with standard 22V10 PLDs. Eight additional configurations per macrocell (a total of 12) are also available by using the "+" software/programming option (i.e., 22CV10AZ+). The additional macrocell configurations allow more logic to be put into every device, potentially reducing the design's component count and lowering the power requirements even further. Development and programming support for the PEELTM22CV10AZ is provided by popular third-party programmers and development software. ICT also offers free PLACE development software and a low-cost development system (PDS-3).
Figure 19 Pin Configuration
I/CLK I I I I I I I I I I GND 1 2 3 4 5 6 7 8 9 10 11 12 24 23 22 21 20 19 18 17 16 15 14 13 VCC I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I
Figure 19 Block Diagram
DIP
TSSOP
PLCC
SOIC
1 of 10
PEELTM 22CV10AZ
(OPTIONAL)
132 0
ASYNCHRONOUS CLEAR (TO ALL MACROCELLS)
2
9
MACRO CELL
I/O
(27)
I/CLK
(2)
10
20
MACRO CELL
I/O
(26)
I
(3)
21
MACRO CELL
33
I/O
(25)
I
(4)
34
MACRO CELL
48
I/O
(24)
I
49
(5)
MACRO CELL
65
I/O
(23)
I
(6)
66
MACRO CELL
82
I/O
(21)
I
(7)
83
MACRO CELL
97
I/O
(20)
I
(9)
98
MACRO CELL
110
I/O
(19)
I
(10)
111
121
MACRO CELL
I/O
(18)
I
(11)
124
130
I
(12)
131
MACRO CELL
SYNCHRONOUS PRESET (TO ALL MACROCELLS)
I/O
(17)
I
(13) (16)
I
Figure 21 PEELTM22CV10AZ Logic Array Diagram
2 of 10
PEELTM 22CV10AZ
Function Description
The implements logic functions as sum-of-products expressions in a programmable-AND/fixed-OR logic array. Userdefined functions are created by programming the connections of input signals into the array. User-configurable output structures in the form of I/O macrocells further increase logic flexibility. W hen programming the PEELTM22CV10AZ, the device programmer first performs a bulk erase to remove the previous pattern. The erase cycle opens every logical connection in the array. The device is configured to perform the user-defined function by programming selected connections in the AND array. (Note that PEELTM device programmers automatically program all of the connections on unused product terms so that they will have no effect on the output function).
Architecture Overview
The architecture is illustrated in the block diagram of Figure 19. Twelve dedicated inputs and 10 I/Os provide up to 22 inputs and 10 outputs for creating logic functions (see Figure 21). At the core of the device is a programmable electrically-erasable AND array that drives a fixed OR array. With this structure, the PEELTM22CV10AZ can implement up to 10 sum-of-products logic expressions. Associated with each of the ten OR functions is an I/O macrocell that can be independently programmed to one of four different configurations in standard 22V10 mode, or any one of 12 configurations using the special "Plus" mode. The programmable macrocells allow each I/O to be used to create sequential or combinatorial logic functions of activehigh or active-low polarity, while providing three different feedback paths into the AND array.
Variable Product Term Distribution
The PEELTM22CV10AZ provides 120 product terms to dr ive the 10 OR functions. These product terms are distributed among the outputs in groups of 8, 10, 12, 14, and 16 to form logical sums (see Figure 21). This distribution allows optimum use of the device resources.
Programmable I/O Macrocell
The unique twelve-configuration output macrocell provides complete control over the architecture of each output. The ability to configure each output independently lets you to tailor the configuration of the PEELTM22CV10AZ to the precise requirements of your design.
Macrocell Architecture
Each I/O macrocell, as shown in Figure 20, consists of a Dtype flip-flop and two signal-select multiplexers. The configuration of the macrocell is determined by four EEPROM bits that control the multiplexers. These bits determine the output polarity, output type (registered or non-registered) and input-feedback path (bidirectional I/O, combinatorial feedback). Refer to Table 1. for details. Four of these macrocells duplicate the functionality of the industry-standard PAL22V10. (See Figure 21 and Table 1.)
AND/OR Logic Array
The programmable AND array of the PEELTM22CV10AZ (shown in Figure 21) is formed by input lines intersecting product terms. The input lines and product terms are used as follows:
s
44 Input Lines: 24 input lines carry the true and complement of the signals applied to the 12 input pins 20 additional lines carry the true and complement values of feedback or input signals from the 10 I/Os
s
133 Product Terms: 120 product terms (arranged in 2 groups of 8, 10, 12, 14, and 16) are used to form sum of product functions 10 output enable terms (one for each I/O) 1 global synchronous preset term 1 global asynchronous clear term 1 programmable clock term
Figure 20 Block Diagram of the PEELTM22CV10A I/O Macrocell
At each input-line/product-term intersection, there is an EEPROM memory cell that determines whether or not there is a logical connection at that intersection. Each product term is essentially a 44-input AND gate. A product term that is connected to both the true and complement of an input signal will always be FALSE and therefore will not affect the OR function that it drives. When all the connections on a product term are opened, a "don't care" state exists and that term will always be TRUE.
3 of 10
|
|
