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Part: 2308
Category:
Timing Circuits
-> PLL (Phase locked loop)
Description: 3.3V Zero Delay Clock Multiplier
Company: Integrated Device Technology, Inc.
Datasheet: Download 2308 datasheet File size : 125 kB
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Datasheet text preview:
IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK MULTIPLIER
FEATURES: DESCRIPTION:
IDT2308
· Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 133MHz operating frequency · Distributes one clock input to two banks of four outputs · Separate output enable for each output bank · External feedback (FBK) pin is used to synchronize the outputs to the clock input · Output Skew <200 ps · Low jitter <200 ps cycle-to-cycle · 1x, 2x, 4x output options (see table): IDT2308-1 1x IDT2308-2 1x, 2x IDT2308-3 2x, 4x IDT2308-4 2x IDT2308-1H, -2H, and -5H for High Drive · No external RC network required · Operates at 3.3V VDD · Available in SOIC and TSSOP packages
The IDT2308 is a high-speed phase-lock loop (PLL) clock multiplier. It is designed to address high-speed clock distribution and multiplication applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2308 has two banks of four outputs each that are controlled via two select addresses. By proper selection of input addresses, both banks can be put in tri-state mode. In test mode, the PLL is turned off, and the input clock directly drives the outputs for system testing purposes. In the absence of an input clock, the IDT2308 enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25µA. The IDT2308 is available in six unique configurations for both prescaling and multiplication of the Input REF Clock. (See available options table.) The PLL is closed externally to provide more flexibility by allowing the user to control the delay between the input clock and the outputs. The IDT2308 is characterized for both Industrial and Commercial operation.
FUNCTIONAL BLOCK DIAGRAM
(-3, -4) FBK REF 16 1 2 (-5) 2 PLL 3 2 CLKA1
CLKA2
14 CLKA3 15 CLKA4
S2 S1
8 9 Control Logic (-2, -3) 2 6 CLKB1 7
CLKB2
10 CLKB3 11 CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
c 2003 Integrated Device Technology, Inc.
APRIL 2003
DSC 5173/6
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDD Rating Supply Voltage Range Input Voltage Range (REF) Input Voltage Range (except REF) IIK (VI VDD) IO (VO = 0 to VDD) VDD or GND TA = 55°C (in still air)(3) TSTG Operating Storage Temperature Range Commercial Temperature Range Industrial Temperature Range -40 to +85 °C 65 to +150 0 to +70 °C °C Continuous Current Maximum Power Dissipation ±100 0.7 mA W Input Clamp Current Terminal Voltage with Respect to GND (inputs VIH 2.5, VIL 2.5) Continuous Output Current ±50 mA Max. 0.5 to +4.6 0.5 to +5.5 0.5 to VDD+0.5 50 ±50 mA mA Unit V V V VI (2) VI
REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2
1 2 3 4 5 6 7 8
16 15 14 13 12 11 10 9
FBK CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
SOIC/ TSSOP TOP VIEW
Temperature Operating Temperature
PIN DESCRIPTION
Pin Number REF
(1)
Functional Description Input Reference Clock, 5 Volt Tolerant Input Clock Output for Bank A Clock Output for Bank A 3.3V Supply Ground Clock Output for Bank B Clock Output for Bank B Select Input, Bit 2 Select Input, Bit 1 Clock Output for Bank B Clock Output for Bank B Ground 3.3V Supply Clock Output for Bank A Clock Output for Bank A PLL Feedback Input
1 2 3 4 5
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3 . The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
C L K A 1 (2) CLKA2 VDD GND CLKB1 S2(3) S1(3) CLKB3 CLKB4 GND VDD C L K A 3 (2) C L K A 4 (2) FBK
(2) (2) (2) (2)
6 7 8 9 10 11 12 13 14 15 16
C L K B 2 (2)
APPLICATIONS:
· · · · ·
SDRAM Telecom Datacom PC Motherboards/Workstations Critical Path Delay Designs
NOTES: 1 . Weak pull down. 2 . Weak pull down on all outputs. 3 . Weak pull ups on these inputs.
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE(1) SELECT INPUT DECODING
S2 L L H H
NOTE: 1 . H = HIGH Voltage Level L = LOW Voltage Level
S1 L H L H
CLK A Tri-State Driven Driven Driven
CLK B Tri-State Tri-State Driven Driven
Output Source PLL PLL REF PLL
PLL Shut Down Y N Y N
AVAILABLE OPTIONS FOR IDT2308
Device IDT2308-1 IDT2308-1H IDT2308-2 IDT2308-2 IDT2308-2H IDT2308-2H IDT2308-3 IDT2308-3 IDT2308-4 IDT2308-5H Feedback From Bank A or Bank B Bank A or Bank B Bank A Bank B Bank A Bank B Bank A Bank B Bank A or Bank B Bank A or Bank B Bank A Frequency Reference Reference Reference 2 x Reference Reference 2 x Reference 2 x Reference 4 x Reference 2 x Reference Reference/2 Bank B Frequency Reference Reference Reference/2 Reference Reference/2 Reference Reference or Reference(1) 2 x Reference 2 x Reference Reference/2
NOTE: 1 . Output phase is indeterminant (0° or 180° from input clock).
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ZERO DELAY AND SKEW CONTROL
To close the feedback loop of the IDT2308, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust the input-output delay. For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. If input-output delay adjustments are required, use the Output Load Difference Chart to calculate loading differences between the feedback output and remaining outputs. Ensure the outputs are loaded equally, for zero output-output skew.
REF TO CLKA/CLKB DELAY vs. OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS
1500
1000
REF to CLKA/CLKB Delay (ps)
500
0
-30
-25
-20
-15
-10
-5
0
5
10
15
20
25
30
-500
-1000
-1500
OUTPUT LOAD DIFFERENCE BETWEEN FBK PIN AND CLKA/CLKB PINS ( pF)
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IDT2308 3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
OPERATING CONDITIONS- COMMERCIAL
Symbol VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance below 100MHz Load Capacitance from 100MHz to 133MHz Input Capacitance
(1)
Parameter
Test Conditions
Min. 3 0 -- -- --
Max. 3.6 70 30 15 7
Unit V
°C
pF pF pF
NOTE: 1 . Applies to both REF and FBK.
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol VIL VIH IIL IIH VOL VOH IDD_PD Parameter Input LOW Voltage Level Input HIGH Voltage Level Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Power Down Current VIN = 0V VIN = VDD IOL = 8mA (-1, -2, -3, -4) IOL = 12mA (-1H, -2H, -5H) IOH = -8mA (-1, -2, -3, -4) IOH = -12mA (-1H, -2H, -5H) REF = 0MHz (S2 = S1 = H) 100MHz CLKA (-1, -2, -3, -4) 100MHz CLKA (-1H, -2H, -5H) IDD Supply Current Unloaded Outputs Select Inputs at VDD or GND 66MHz CLKA (-1, -2, -3, -4) 66MHz CLKA (-1H, -2H, -5H) 33MHz CLKA (-1, -2, -3, -4) 33MHz CLKA (-1H, -2H, -5H) -- -- -- -- -- -- -- -- -- -- -- -- -- -- 12 45 70 32 50 18 30 mA µA 2.4 -- -- V Conditions Min. -- 2 -- -- -- Typ.(1) -- -- -- -- -- Max. 0.8 -- 50 100 0.4 Unit V V µA µA V
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Others parts begin by 23
23-1 23-2
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