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Details, datasheet, quote on part number:2309
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| Part: | 2309 |
| Category: | Timing Circuits => PLL (Phase locked loop) |
| Description: | 3.3V Zero Delay Clock Buffer |
| Company: | Integrated Device Technology, Inc. |
| Datasheet: | Download 2309 datasheet File size : 138 kB |
| Request For quote: | Find where to buy 2309
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Datasheet text preview:
IDT2309 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK BUFFER
FEATURES: DESCRIPTION:
IDT2309
· Phase-Lock Loop Clock Distribution · 10MHz to 133MHz operating frequency · Distributes one clock input to one bank of five and one bankd of four outputs · Separate output enable for each output bank · Output Skew < 250ps · Low jitter <200 ps cycle-to-cycle · IDT2309-1 for Standard Drive · IDT2309-1H for High Drive · No external RC network required · Operates at 3.3V VDD · Available in SOIC and TSSOP packages
The IDT2309 is a high-speed phase-lock loop (PLL) clock buffer, designed to address high-speed clock distribution applications. The zero delay is achieved by aligning the phase between the incoming clock and the output clock, operable within the range of 10 to 133MHz. The IDT2309 is a 16-pin version of the IDT2305. The IDT2309 accepts one reference input, and drives two banks of four low skew clocks. The -1H version of this device operates at up to 133MHz frequency and has higher drive than the -1 device. All parts have on-chip PLLs which lock to an input clock on the REF pin. The PLL feedback is on-chip and is obtained from the CLKOUT pad. In the absence of an input clock, the IDT2309 enters power down, and the outputs are tri-stated. In this mode, the device will draw less than 25µA. The IDT2309 is characterized for both Industrial and Commercial operation.
FUNCTIONAL BLOCK DIAGRAM
16 CLKOU T
1 R EF
PLL
2
C LK A 1
3
CLKA2
14
CLKA3
15
CLKA4
S2 S1
8 9 C o n tr o l L o g ic
6
CLKB1
7
C LK B 2
10
C LK B 3
11
C LK B 4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
c 2002 Integrated Device Technology, Inc.
NOVEMBER 2002
DSC 5175/2
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IDT2309 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATION
REF CLKA1 CLKA2 VDD GND CLKB1 CLKB2 S2 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9
SOIC/ TSSOP TOP VIEW
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Rating Supply Voltage Range Input Voltage Range (REF) Input Voltage Range (except REF) IIK (VI < 0) IO (VO = 0 to VDD) VDD or GND TA = 55°C (in still air) TSTG Operating Temperature Operating Temperature
(3)
Max. 0.5 to +4.6 0.5 to +5.5 0.5 to VDD+0.5 50 ±50 ±100 0.7 65 to +150 0 to +70 -40 to +85
Unit V V V mA mA mA W °C °C °C
CLKOUT CLKA4 CLKA3 VDD GND CLKB4 CLKB3 S1
VDD VI (2) VI
Input Clamp Current Continuous Output Current Continuous Current Maximum Power Dissipation Storage Temperature Range Commercial Temperature Range Industrial Temperature Range
APPLICATIONS:
· · · · · SDRAM Telecom Datacom PC Motherboards/Workstations Critical Path Delay Designs
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3 . The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750 mils.
PIN DESCRIPTION
Pin Name REF
(1)
Pin Number 1 2 3 4, 13 5, 12 6 7 8 9 10 11 14 15 16
Type IN Out Out PWR GND Out Out IN IN Out Out Out Out Out
Functional Description Input reference clock, 5 Volt tolerant input Output clock for bank A Output clock for bank A 3.3V Supply Ground Output clock for bank B Output clock for bank B Select input Bit 2 Select input Bit 1 Output clock for bank B Output clock for bank B Output clock for bank A Output clock for bank A Output clock, internal feedback on this pin
CLKA1(2) CLKA2 VD D GND CLKB1(2) CLKB2(2) S2(3) S1
(3) (2)
CLKB3(2) CLKB4(2) CLKA3(2) CLKA4
(2)
C L K O U T (2)
NOTES: 1 . Weak pull down. 2 . Weak pull down on all outputs. 3 . Weak pull ups on these inputs.
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IDT2309 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
S2 L L H H S1 L H L H CLKA Tri-State Driven Driven Driven CLKB Tri-State Tri-State Driven Driven C L K O U T (2) Driven Driven Driven Driven Output Source PLL PLL REF PLL PLL Shut Down N N Y N
NOTES: 1 . H = HIGH Voltage Level. L = LOW Voltage Level 2 . This output is driven and has an internal feedback for the PLL. The load on this ouput can be adjusted to change the skew between the REF and the output.
DC ELECTRICAL CHARACTERISTICS - COMMERCIAL
Symbol VIL VIH IIL IIH VOL VOH IDD_PD IDD Parameter Input LOW Voltage Level Input HIGH Voltage Level Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Power Down Current Supply Current VIN = 0V VIN = VDD Standard Drive High Drive Standard Drive High Drive REF = 0MHz (S2 = S1 = H) Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND IOL = 8mA IOL = 12mA (-1H) IOH = -8mA IOH = -12mA (-1H) -- -- 12 32 µA mA 2.4 -- V Conditions Min. -- 2 -- -- -- Max. 0.8 -- 50 100 0.4 Unit V V µA µA V
OPERATING CONDITIONS - COMMERCIAL
Symbol VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance < 100MHz Load Capacitance 100MHz - 133MHz Input Capacitance Parameter Min. 3 0 -- -- --
(1,2)
Max. 3.6 70 30 10 7
Unit V
°C
pF pF
SWITCHING CHARACTERISTICS (2309-1) - COMMERCIAL
Symbol t1 Parameter Output Frequency Duty Cycle = t2 ÷ t1 t3 t4 t5 t6A t6B t7 tJ tLOCK Rise Time Fall Time Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Device-to-Device Skew Cycle-to-Cycle Jitter PLL Lock Time
(2)
Conditions 10pF Load 30pF Load Measured at 1.4V, FOUT = 66.66MHz Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured at VDD/2 Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin
Min. 10 10 40 -- -- -- -- 1 -- -- --
Typ. -- -- 50 -- -- -- 0 5 0 -- --
Max. 133 100 60 2.5 2.5 250 ±350 8.7 700 200 1
Unit MHz % ns ns ps ps ns ps ps ms
Delay, REF Rising Edge to CLKOUT Rising Edge(2) Measured at VDD/2 in PLL bypass mode (IDT2309 only)
NOTES: 1 . REF Input has a threshold voltage of VDD/2. 2 . All parameters specified with loaded outputs.
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IDT2309 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
(1,2)
SWITCHING CHARACTERISTICS (2309-1H) - COMMERCIAL
Symbol t1 Parameter Output Frequency Duty Cycle = t2 ÷ t1 Duty Cycle = t2 ÷ t1 t3 t4 t5 t6A t6B t7 t8 tJ tLOCK Rise Time Fall Time Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Delay, REF Rising Edge to CLKOUT Rising Edge Device-to-Device Skew Output Slew Rate Cycle-to-Cycle Jitter PLL Lock Time 10pF Load 30pF Load Measured at 1.4V, FOUT = 66.66MHz Measured at 1.4V, FOUT <50MHz Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured at VDD/2 Conditions
Min. 10 10 40 45 -- -- -- -- 1 -- 1 -- --
Typ. -- -- 50 50 -- -- -- 0 5 0 -- -- --
Max. 133 100 60 55 1.5 1.5 250 ±350 8.7 700 -- 200 1
Unit MHz % % ns ns ps ps ns ps V/ns ps ms
Measured at VDD/2 in PLL bypass mode (IDT2309 only) Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8V and 2V using Test Circuit 2 Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin
NOTES: 1 . REF Input has a threshold voltage of VDD/2. 2 . All parameters specified with loaded outputs.
DC ELECTRICAL CHARACTERISTICS - INDUSTRIAL
Symbol VIL VIH IIL IIH VOL VOH IDD_PD IDD Parameter Input LOW Voltage Level Input HIGH Voltage Level Input LOW Current Input HIGH Current Output LOW Voltage Output HIGH Voltage Power Down Current Supply Current VIN = 0V VIN = VDD Standard Drive High Drive Standard Drive High Drive REF = 0MHz (S2 = S1 = H) Unloaded Outputs at 66.66MHz, SEL inputs at VDD or GND IOL = 8mA IOL = 12mA (-1H) IOH = -8mA IOH = -12mA (-1H) -- -- 25 35 µA mA 2.4 -- V Conditions Min. -- 2 -- -- -- Max. 0.8 -- 50 100 0.4 Unit V V µA µA V
OPERATING CONDITIONS - INDUSTRIAL
Symbol VDD TA CL CIN Supply Voltage Operating Temperature (Ambient Temperature) Load Capacitance < 100MHz Load Capacitance 100MHz - 133MHz Input Capacitance Parameter Min. 3 -40 -- -- -- Max. 3.6 +85 30 10 7 pF Unit V
°C
pF
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IDT2309 3.3V ZERO DELAY CLOCK BUFFER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
(1,2)
SWITCHING CHARACTERISTICS (2309-1) - INDUSTRIAL
Symbol t1 Parameter Output Frequency Duty Cycle = t2 ÷ t1 t3 t4 t5 t6A t6B t7 tJ tLOCK Rise Time Fall Time Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Delay, REF Rising Edge to CLKOUT Rising Edge Device-to-Device Skew Cycle-to-Cycle Jitter PLL Lock Time 10pF Load 30pF Load Measured at 1.4V, FOUT = 66.66MHz Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured at VDD/2 Conditions
Min. 10 10 40 -- -- -- -- 1 -- -- --
Typ. -- -- 50 -- -- -- 0 5 0 -- --
Max. 133 100 60 2.5 2.5 250 ±350 8.7 700 200 1
Unit MHz % ns ns ps ps ns ps ps ms
Measured at VDD/2 in PLL bypass mode (IDT2309 only) Measured at VDD/2 on the CLKOUT pins of devices Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin
NOTES: 1 . REF Input has a threshold voltage of VDD/2. 2 . All parameters specified with loaded outputs.
SWITCHING CHARACTERISTICS (2309-1H) - INDUSTRIAL
Symbol t1 Parameter Output Frequency Duty Cycle = t2 ÷ t1 Duty Cycle = t2 ÷ t1 t3 t4 t5 t6A t6B t7 t8 tJ tLOCK Rise Time Fall Time Output to Output Skew Delay, REF Rising Edge to CLKOUT Rising Edge Delay, REF Rising Edge to CLKOUT Rising Edge Device-to-Device Skew Output Slew Rate Cycle-to-Cycle Jitter PLL Lock Time 10pF Load 30pF Load Measured at 1.4V, FOUT = 66.66MHz Measured at 1.4V, FOUT <50MHz Measured between 0.8V and 2V Measured between 0.8V and 2V All outputs equally loaded Measured at VDD/2 Conditions
(1,2)
Min. 10 10 40 45 -- -- -- -- 1 -- 1 -- --
Typ. -- -- 50 50 -- -- -- 0 5 0 -- -- --
Max. 133 100 60 55 1.5 1.5 250 ±350 8.7 700 -- 200 1
Unit MHz % % ns ns ps ps ns ps V/ns ps ms
Measured at VDD/2 in PLL bypass mode (IDT2309 only) Measured at VDD/2 on the CLKOUT pins of devices Measured between 0.8V and 2V using Test Circuit 2 Measured at 66.66MHz, loaded outputs Stable power supply, valid clock presented on REF pin
NOTES: 1 . REF Input has a threshold voltage of VDD/2. 2 . All parameters specified with loaded outputs.
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