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Details, datasheet, quote on part number:49C465
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Datasheet text preview:
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
FEATURES:
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IDT49C465 IDT49C465A
DESCRIPTION:
The IDT49C465/A is a 32-bit, two-data bus, Flow-thruEDC unit. The chip provides single-error correction and two and three bit error detection of both hard and soft memory errors. It can be expanded to 64-bit widths by cascading two units, without the need for additional external logic. The Flow-thruEDC has been optimized for speed and simplicity of control. The EDC unit has been designed for use in either of two configurations in an error correcting memory system. The bidirectional configuration is most appropriate for systems using bidirectional memory buses. A second system configuration utilizes external octal buffers, and is well-suited for systems using memory with separate I/O buses. The IDT49C465/A supports partial word writes, pipelining, and error diagnostics. It also provides parity protection for data on the system side.
32-bit wide Flow-thruEDCTM unit, cascadable to 64 bits Single-chip 64-bit Generate Mode Separate system and memory buses On-chip pipeline latch with external control Supports bidirectional and common I/O memories Corrects all single-bit errors Detects all double-bit errors and some multiple bit errors Error Detection Time -- 12ns Error Correction Time -- 14ns On chip diagnostic registers Parity generation and checking on system data bus Low power CMOS -- 100mA typical at 20MHz 144-pin PGA and PQFP packages
SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM
M D 0 -3 1
C o rre ct Lo g ic MD L a tc h M em ory C h ec k b it G e n e r a to r
S yn d ro m e G e n e r a to r
MLE C B I0 -7
C h ec k b it L atch
ERR
E x p a n s io n L og ic
M ux
D e te c t L og ic
MERR
P C B I0- 7 S D 0 -3 1
P ip e l in e L atch
CONTROL
CONTROL B yte M ux
SD L atc h
SLE
S y s te m C h e c k b it G e n e r a to r
M ux
C B O 0 -7
PLE
CONTROL
CONTROL
COMMERCIAL TEMPERATURE RANGE
c 1999 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
NOVEMBER 2000
1
DSC-2552/9
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
72 V cc SD 5 SD 6 SD 7 SD 8 SD 9 S D 10 S D 11 GND BE1 S D 12 S D 13 S D 14 S D 15 SLE PLE SO E GND S D 16 S D 17 S D 18 S D 19 BE2 S D 20 S D 21 S D 22 GND S D 23 S D 24 S D 25 S D 26 S D 27 BE3 S D 28 V cc V cc 73
V cc SD 4 BE0 SD 3 SD 2 SD 1 SD 0 P C B I7 P C B I6 P C B I5 P C B I4 P C B I3 P C B I2 P C B I1 P C B I0 C O D E ID 1 C O D E ID 2 GND GND MODE 1 MODE 0 MERR ER R SYO7 SYO6 SYO5 SYO4 GND SYO3 SYO2 SYO1 SYO0 MD0 MD1 MD2 V cc
37 36 V cc V cc MD3 MD4 MD5 MD6 MD7 MD8 MD9 GND M D 10 M D 11 M D 12 M D 13 M D 14 M D 15 M LE MOE GND M D 16 M D 17 M D 18 M D 19 M D 20 M D 21 M D 22 M D 23 GND M D 24 M D 25 M D 26 M D 27 M D 28 M D 29 M D 30 V cc
49C465Y P Q 1 4 4 -2
108 109 144
1
V cc S D 29 S D 30 S D 31 CBO 0 CBO 1 CBO 2 CBO 3 CBOE CBO 4 CBO 5 CBO 6 CBO 7 PSEL PE RR P3 P2 GND GND P1 P0 MODE 2 SYN CLK SCLKE N C LE A R C B I0 C B I1 C B I2 C B I3 GND C B I4 C B I5 C B I6 C B I7 M D 31 V cc
PQFP TOP VIEW 2
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
15 Vcc SD2 P C B I6 P C B I5 P C B I3 CODE CODE MODE ME RR ERR ID 1 ID 2 1 MODE SYO6 0 GND SYO7 SYO5 SYO3 SYO1 MD1 Vcc
14
SD6
SD4
SD 1
P C B I7 P C B I4 P C B I1 P C B I0
SYO4 SY O2 M D0
MD2
Vcc
MD5
13
SD9
SD5
BE0
SD3
SD0
P C B I2 G N D
GND SYO0
Vcc
MD3
MD6
MD9
12
S D 11
SD7
Vcc
MD4
MD8
GND
11
S D 12
S D 10
SD 8
M D 7 M D 10
M D 11
10
S D 15
BE1
GND
M D 12 M D 13
M D 15
9
SLE SO E
S D 13 PLE
S D 14 GND G 14 4 -2
M O E M D 14 G N D M D 17
MLE
8
M D 16
7
S D 17
S D 19
S D 16
M D 20 M D 21
M D 18
6
S D 18
BE2
S D 20
G N D M D 23
M D 19
5
S D 21
S D 22
S D 25 NC*
M D 27 M D 25
M D 22
4
GND
S D 24
BE3
Vcc S C LK GND EN
M D 28
M D 24
3
S D 23
S D 26
S D 28
Vcc
C B 00 C B O E C B 07 G N D
GND
CB16
C B 1 7 M D 30
M D 26
2
S D 27
Vcc
S D 29
S D 31 C B 0 2
C B 04
CB06
P3
MODE SYNCB10 2 CLK P1 J P0 K
CB13
C B 1 4 M D 31
M D 29
1
Vcc A
S D 30 B
CB 01 C
C B 03 C B 05 D E
PSEL PERR F G
P2
C LE A R C B 11 L M
CB12 CB15 N P
Vcc R
H
* = Tied to Vcc internally
PGA (CAVITY UP) TOP VIEW 3
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
DETAILED FUNCTIONAL BLOCK DIAGRAM
D a s h e d L i n e = Diagnostic path P C B I0 - 7
ERR MERR
ER R O R D E T EC T
8
M U X
IN T E R N A L F IN A L S YN D R O M E
8
8
8
8
S Y O 0 -7
8
M U X
SY N D R OM E G ENERATO R
8 8
M U X
CHECK B IT LATC H
8
M U X
8
C B I0 - 7
PLE SO E B E 0 -3
8
MD C H E C K B IT G EN E R AT O R MD LAT C H
M LE
ER R O R C O R R EC T
M U X 1 OF 4 BY T E S P IP E LAT C H
E R R O R D A T A LATCH CLEAR M D 0-31 D IA G N O S T IC LAT C H ES I N T E R N A L SYN C L K
S D 0 -31
BYTE M U X
SD LAT C H MOE SL E PS EL B E 0-3
4
4 4 4
P A R IT Y GEN
P 0- 3
SD C H E C K B IT GENERATOR
8
P A R IT Y CHE CK M U X SD C H E C K B IT G EN E R AT O R
M U X
8
8
C B O 0-7
C BO E
PE R R
8
/E R R
8
I N T E R N A L SYN C L K SY N C LK SC LKE N CLEAR
P C B I0 - 7
C O D E ID 0,1 M O D E 0-2
2
3
CONTRO L L O G IC
4
IDT49C465/A 32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
SYSTEM CONFIGURATIONS
The IDT49C465 EDC unit can be used in various configurations in an EDC system. The basic configurations are shown below. Figure 1 illustrates a bidirectional configuration, which is most appropriate for systems using bidirectional memory buses. It is the simplest configuration to understand and use. During a correction cycle, the corrected data word can be simultaneously output on both the system bus and memory bus. During partial-word-write operations, the new bytes are internally combined with the corrected old bytes for checkbit memory. Partial word-write bytes are combined externally for writing and checkbit generation. Figure 3 illustrates a third configuration which uses external buffers and is also well-suited for systems using memory with separate I/O
MEMORY IN P U T BUS
C H E C K B IT I /O
MEMORY O U T P U T BUS
CPU I/ O
SD
MD
M EM ORY I/ O
CBO SD
CBI MD EDC
EDC
CBI C H E C K B IT S CBO
E X T . BUFFER C P U BUS
E X T . BUFFER
Figure 1. Common I/O Configuration
Figure 3. Bypassed Separate I/O Configuration
generation and writing to memory. Figure 2 illustrates a separate I/O configuration. This is appropriate for systems using separate I/O memory buses. This configuration allows separate input and output memory buses to be used. Corrected data is output on the SD outputs for the system and for re-write to
E X T . BUFFER
buses. Since data from memory does not need to pass through the part on every cycle, the EDC system may operate in "bus-watch" mode. As in the separate I/O configuration, corrected data is output on the SD outputs. Figure 4 illustrates the single-chip generate-only mode for the very fast 64-bit checkbit generation in systems that use separate checkbitgenerate and detect-correct units. If this is not desired, 64-checkbit generation and correction can be done with just two EDC units. 64-bit correction is also straightforward, fast, and requires no extra hardware for the expansion.
CHECK B IT S OUT MEMO RY IN P U T BUS C BO C BI MEMO RY IN P U T BUS CHECK B IT S IN MEMO RY O U T P U T BUS
CPU
M EMORY IN P U T S
SD MD EDC
B UF FER
MEMO RY O UTP UTS
6 4 -B IT G EN . ON LY
LO W ER DATA
U PP ER D ATA
EDC
ED C B UF FER B U FFE R
EDC B UF FER
CBI CBO
Figure 2. Separate I/O Configuration
C H E C K B IT S
C P U BUS
Figure 4. Separate generate/Correction Units with 64-Bit Checkbit Generation
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