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Details, datasheet, quote on part number:49C466
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Datasheet text preview:
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
FEATURES:
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IDT49C466 IDT49C466A
DESCRIPTION:
The IDT49C466/A 64-bit Flow-thruEDC is a high-speed error detection and correction unit that ensures data integrity in memory systems. The flowthru architecture, with separate system and memory data buses, is ideally suited for pipelined memory systems. Implementing a modified Hamming code, the IDT49C466/A corrects all single bit hard and soft errors, and detects all double bit errors. The read/ write FIFOs can store up to sixteen words. FIFO full and empty flags indicate whether additional data can be written to or read from the EDC. Check bit generation for partial word writes on byte boundaries is supported on the IDT49C466/A. Diagnostic features include a check bit register, syndrome registers, a four bit error counter which logs up to fifteen errors, and an error data register which stores the complete error data word. Parity can be generated and checked on the system bus by the IDT49C466/A.
64-bit wide Flow-thruEDCTM Separate System and Memory Data Input/Output Buses · Error Detect Time: 10ns · Error Correct Time: 15ns Corrects all single bit errors; Detects all double bit errors and some multiple bit errors Configurable 16-deep bus read/write FIFOs with flags Simultaneous check bit generation and correction of memory data Supports partial word writes on byte boundaries Low noise output Sophisticated error diagnostics and error logging Parity generation on system data bus 208-pin Plastic Quad Flatpack
FUNCTIONAL BLOCK DIAGRAM
D IA G N O S T IC & STATUS REGISTERS ERR MERR C H E C K -B IT COMPARATO R & SYNDRO M E GENERATOR & ERROR DETECTOR M U X ERROR CORRECT
M U X
R E A D BUFFER 1 6 W O R D S BY 64
MD C H E C K -B I T GENERATOR
MD C H K -B IT LATCH
C B I0 - 7
MD LATCH OUT
MD LATCH IN
S D 0 -6 3
W R I T E BACK PATH M D 0 -6 3 SD LATCH IN M U X B Y T E M U X
SD LATCH OUT
W R IT E BUFFER 1 6 W O R D S BY 72 P A R IT Y GENERATE & PARITY CHECK
SD C H E C K - B IT GENERATOR
SD C H K -B IT LATCH
C B S Y N 0 -7
P A R IT Y P 0 -7
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
c 1999 Integrated Device Technology, Inc.
FEBRUARY 2000
1
DSC-2617/9
8 8 8 MUX 8 MD C H E C K B IT LA TC H 8 SYN DR O ME GEN ER ATO R ERROR D E TE CT C B I0- 7
ERR
ME RR
MDOLE
M O D E BIT 2
M CLK
D IA G N O S T I C REGISTERS 0-7 C H K B IT C H K B IT ( O N 1ST ERROR) SY N D R O M E ( O N 1ST ERROR) E R R COUNT 2 8-2 9 E R R TYPE ERR MERR C LE A R
FR O M MODE REG IST ER
MD C H E C K B IT G EN ER ATO R
RBEN
8-1 5 1 6-2 3 24- 27
MUX
R S 0- 1
M D IL E
RBREN
RBSEL
RBEF
C ON TR O L
MUX
SYN C LK
RB FF
3 0-3 7 SY N D R O M E ( O N EVERY ERROR) E R R O R DAT A
RBHF R E A D FIFO 6 4 W ID E ERRO R CO RRECT
SO E
MUX
R W B D (BIT 4, MODE REG)
0
MD LATCH OUT
W R IT E B A C K PATH
1
DEMUX
1 S C LK
MD LA TC H IN M D 0 -6 3
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
S D 0 -63
MUX
SD LATCH IN
0
S D IL E
B Y T E MU X
SD LA TC H O UT MOE S D O LE
S D 0 -15 W R I T E FIFO 72 W ID E
C O N TR O L 1
MUX
R E G IS T E R MODE B E 0 -7
C H E C K B I T IN J E C T I O N M O D E
B E 0 -7
8
R S 0 -1 R W B D (BIT 4, MODE REG)
W BR EN
8
1
8 P A R IT Y G EN P A R IT Y CHECK
4 M O D E BIT 5
MUX
W BEF
W B FF
2
8
0 M C LK
C BSEL
0
MEN
SC LK
SD C H E C K B IT G EN E RA TO R
W BEN
SD CHE CK B IT LA TC H
C B S Y N 0-7
W BSEL
P 0 -7
8
PER R
M D TO SD PATH S D TO MD PATH D I A G N O S T I C PATH
POWER SU P P LY
Vcc G ND
17
COMMERCIAL TEMPERATURE RANGE
49C466/A 64-Bit Flow-ThruEDC
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
GND MD54 MD53 MD52 MD51 MD50 MD49 MD48 MD47 MD46 MD45 MD44 MD43 MD42 MD41 MD40 MD39 MD38 MD37 MD36 MD35 MD34 MD33 MD32 SDO LE MOE M D IL E MD31 GND MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 GND MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 VC C
1
20 8
GND M D55 M D5 6 M D5 7 M D5 8 M D5 9 M D6 0 M D6 1 M D62 M D6 3 CBSYN7 CBSYN6 CBSYN5 CBSYN4 GND CB SY N3 CB SY N2 CBSYN1 CB SY N0 VCC GND WBSEL CBSEL W BREN GND WBEN S Y N C LK W BFF W BEF SD63 SD62 SD61 SD60 P7 BE7 GND SD59 SD58 SD57 SD56 SD55 SD54 SD53 SD52 P6 BE6 SD51 SD50 SD49 SD48 SD47 VC C
1 57 1 56
P Q 20 8-2
52 53
1 05 1 04
GND SD46 SD45 SD44 BE 5 P5 SD43 SD42 SD41 SD40 SD39 SD38 SD37 SD36 BE 4 GND P4 SD35 SD34 SD33 SD32 PE RR MCLK M D O LE RS 1 MEN GND RS_0 S D IL E SC LK SO E SD31 SD30 SD29 SD28 BE 3 P3 SD27 SD26 SD25 SD24 SD23 SD22 SD21 SD20 BE 2 P2 SD19 SD18 SD17 SD16 GND
GND MD9 MD8 M D7 M D6 M D5 M D4 M D3 M D2 MD1 M D0 ERR M ERR C B I7 C B I6 C BI5 CB I4 C BI3 GND C B I2 C BI1 C B I0 RBEN RBREN RBSEL GND VCC RBHF RBEF RB FF SD0 SD1 SD2 SD 3 GND P0 BE0 SD4 SD5 SD6 SD7 SD8 SD9 SD1 0 SD11 BE 1 P1 SD12 SD1 3 SD14 SD15 GND
PQFP TOP VIEW 3
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name Data Buses SD0-63 I/O System Data Bus: is a bidirectional 64-bit bus interfacing to the system or CPU. When System Output Enable, SOE, is HIGH or Byte Enable, BE0-7, is LOW, data can be input. When System Output Enable, SOE, is LOW and Byte Enable, BE0-7, is HIGH, the SD bus output drivers are enabled. Memory Data Bus: is a bidirectional 64-bit bus interfacing to the memory. During a read cycle, (MOE HIGH) memory data is input for error detection and correction. Data is output on the Memory Data Bus, when MOE is LOW. Check Bit Inputs: interface to the check bit memory. Check Bit/Syndrome Output: when MOE is LOW, the generated check bits are output. When CBSEL is HIGH and MOE is HIGH, the syndrome bits are output. The bus is tristated when MOE = 1 and CBSEL = 0. Parity for bytes 0 to 7: these pins are parity inputs when the corresponding Byte Enable (BE) is LOW or SOE is HIGH, and are used to generate the parity error signal (PERR). These pins are outputs when the corresponding Byte Enable (BE) is HIGH and SOE is LOW. System Output Enable: enables system data bus output drivers if the corresponding Byte Enable (BE0-7) is HIGH. Byte Enable: is used along with SOE to enable the System Data outputs for a particular byte. For example, if BE1 is HIGH, the System data outputs for byte 1 (SD8-15) are enabled. The BE0-7 pins also control the byte mux. If a particular BE is HIGH during a memory read cycle, that byte is fed back to the memory data bus. This is used during partial word write operations and writing corrected data back to memory. Memory Output Enable: when LOW, enables the output buffers of the memory data bus (MD) and CBSYN bus. It also controls the CBSYN mux. When LOW, checkbits are selected, when HIGH, syndrome is selected. Memory Data Input Latch Enable: on the HIGH-to-LOW transition, latches MD and CBI in MD input latch and MD check bit latch respectively. The latches are transparent when MDILE is HIGH. Memory Data Output Latch Enable: latches data in the MD output latch on the LOW-to-HIGH transition of MDOLE. When MDOLE is LOW, the MD output latch is transparent. System Data Output Latch Enable: latches data in the SD output latch and the SD checkbit latch on the LOW-to-HIGH transition of SDOLE. The latch is transparent when SDOLE is LOW. System Data Input Latch Enable: latches SD in the SD input latch on the HIGH-to-LOW transition. When SDILE is HIGH, the SD input latch is transparent. Write FIFO Select: when HIGH, the write FIFO is selected. When WBSEL is LOW, the SD input latch is selected. Write FIFO Enable: when LOW, allows SD data to be written to the write FIFO on the SCLK rising edge. Write FIFO Read Enable: when LOW, allows data to be read from the the write FIFO on MCLK rising edge. Reset and Select pins (read and write FIFO FIFOs) RS1 RS0 Function 0 0 Reset 16-deep FIFO or first 8-deep FIFO 0 1 Reset second 8-deep FIFO 1 0 Select 16-deep FIFO or first 8-deep FIFO 1 1 Select second 8-deep FIFO I/O Description
MD0-63 C B I 0-7 CBSYN 0-7 P0-7
I/O I O I/O
Control Inputs SOE BE0-7 I I
MOE MDILE MDOLE SDOLE SDILE WBSEL WBEN WBREN RS0-1
I I I I I I I I I
4
IDT49C466, IDT49C466A 64-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (cont.)
Pin Name RBSEL RBEN RBREN CBSEL MEN Clock Inputs MCLK SCLK I I Memory Clock: on the LOW-to-HIGH transition of MCLK, memory data is written to the read FIFO when RBEN is LOW. Data is read from the write FIFO when WBREN is LOW, on the LOW-to-HIGH transition of MCLK. System Clock: on the LOW-to-HIGH transition of the SCLK, data is read from the read FIFO when RBREN is LOW. Data on the system data bus is written into the write FIFO when WBEN is LOW on the LOW-to-HIGH transition of SCLK. Clocks data into mode register when MEN is LOW. Syndrome Clock: used to load diagnostic registers. When an error occurs, Error Counter is incremented on the rising SYNCLK edge (up to 15 errors). On the first error after a diagnostic reset, SYNCLK rising edge clocks data into Check Bit, Syndrome, Error Type and Error Data registers. One of the syndrome registers has new data clocked in on every SYNCLK rising edge. Write FIFO Empty Flag: when LOW, indicates that the write FIFO is empty. After a reset, the WBEF goes LOW. Write FIFO Full Flag: when LOW, indicates that the write FIFO is full. After a reset, WBFF goes HIGH. Read FIFO Empty Flag: when LOW, indicates that the read FIFO is empty. After a reset, the RBEF goes LOW. Read FIFO Half-full Flag: when LOW, indicates that there are eight or more data words (in the 16-deep configuration) or four or more data words (in the dual 8-deep configuration) in the read FIFO. The flag will return HIGH when less than eight (or four) data words are in the FIFO. Read FIFO Full Flag: when LOW, indicates that the read FIFO is full. After a reset, RBFF goes HIGH. Error Flag: when ERR is LOW, a data error is indicated. The ERR is not latched internally. Multiple Error Flag: when MERR is LOW, a multiple data error is indicated. The MERR is not latched internally. Parity Error Flag: when LOW, indicates a parity error on the system data bus input. Power Supply Voltage. Ground. I/O I I I I I Description Read FIFO Select: when HIGH, read FIFO is selected (data goes through read FIFO, not MD output latch). When LOW, the MD output latch is selected. Read FIFO Enable: when LOW, allows data to be written into the read FIFO on the LOW-to-HIGH transition of the memory clock. Read FIFO Enable: when LOW, allows data to be read from the read FIFO on the LOW-to-HIGH transition of SCLK. Checkbit Syndrome Output Enable: controls the CBSYN output buffer.When HIGH, the buffer is enabled. When CBSEL is LOW, MOE controls the buffer. Mode Enable Input: when LOW, SD0-15 is loaded into the EDC mode register on the LOW-to-HIGH transition of the SCLK. This pin must be held LOW for the entire SCLK HIGH period, as shown in Figure 4.
SYNCLK
I
Status Outputs WBEF WBFF RBEF RBHF O O O O
RBFF ERR MERR PERR Power Supply VCC GND
O O O O P P
5
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