|Category||Interface and Interconnect|
|Description||Fast CMOS Octal Registered Transceivers|
|Company||Integrated Device Technology, Inc.|
|Datasheet||Download 5429FCT52CTQ datasheet|
Common features: Low input and output leakage 1ľA (max.) CMOS power levels True TTL input and output compatibility VOH = 3.3V (typ.) VOL = 0.3V (typ.) Meets or exceeds JEDEC standard 18 specifications Product available in Radiation Tolerant and Radiation Enhanced versions Military product compliant to MIL-STD-883, Class B and DESC listed (dual marked) Available in DIP, SOIC, SSOP, QSOP, CERPACK and LCC packages Features for B, C and D speed grades High drive outputs (-15mA IOH, 64mA IOL) Power off disable outputs permit "live insertion" Features for A, B and C speed grades Resistor outputs (-15mA IOH, 12mA IOL Com.) (-12mA IOH, 12mA IOL Mil.) Reduced system switching noise
The IDT29FCT52AT/BT/CT/DT and IDT29FCT53AT/BT/ CT are 8-bit registered transceivers built using an advanced dual metal CMOS technology. Two 8-bit back-to-back registers store data flowing in both directions between two bidirectional buses. Separate clock, clock enable and 3-state output enable signals are provided for each register. Both A outputs and B outputs are guaranteed to sink 64mA. The IDT29FCT52AT/BT/CT/DT and IDT29FCT2052AT/BT/ CT are non-inverting options of the IDT29FCT53AT/BT/CT. The IDT29FCT2052AT/BT/CT has balanced drive outputs with current limiting resistors. This offers low ground bounce, minimal undershoot and controlled output fall times-reducing the need for external series terminating resistors. The IDT29FCT2052T part is a plug-in replacement for IDT29FCT52T part.The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Name A0-7 B0-7 CPA I/O Description Eight bidirectional lines carrying the A Register inputs or B Register outputs. Eight bidirectional lines carrying the B Register inputs or A Register outputs. Clock for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal. Clock Enable for the A Register. When CEA is LOW, data is entered into the A Register on the LOW-to-HIGH transition of the CPA signal. When CEA is HIGH, the A Register holds its contents, regardless of CPA signal transitions.
Output Enable for the A Register. When OEB is LOW, the A Register outputs are enabled onto the B0-7 lines. When OEB is HIGH, the B0-7 outputs are in the high-impedance state. Clock for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal.
Clock Enable for the B Register. When CEB is LOW, data is entered into the B Register on the LOW-to-HIGH transition of the CPB signal. When CEB is HIGH, the B Register holds its contents, regardless of CPB signal transitions. Output Enable for the B Register. When OEA is LOW, the B Register outputs are enabled onto the A0-7 lines. OEA is HIGH, the A0-7 outputs are in the high-impedance state. When
NOTE: H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care = No Change = LOW-to-HIGH TransitionNOTE: H = HIGH Voltage Level L = LOW Voltage Level X = Don't Care Z = High Impedance
Symbol Rating Commercial VTERM(2) Terminal Voltage to +7.0 with Respect to GND VTERM(3) Terminal Voltage 0.5 to with Respect to VCC +0.5 GND TA Operating to +70 Temperature TBIAS Temperature to +125 Under Bias TSTG Storage to +125 Temperature PT Power Dissipation 0.5 I OUT DC Output Current to +120 Military to +7.0 Unit V
Symbol Parameter(1) CIN Input Capacitance COUT Output Capacitance Conditions VIN = 0V VOUT = 0V Typ. 6 8 Max. Unit pF 12NOTE: 1. This parameter is measured at characterization but not tested.
2529 lnk 04 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. No terminal voltage may exceed VCC by +0.5V unless otherwise noted. 2. Input and VCC terminals only. 3. Outputs and I/O terminals only.
|Related products with the same datasheet|
|Some Part number from the same manufacture Integrated Device Technology, Inc.|
|5429FCT52CTQB Fast CMOS Octal Registered Transceivers|
|59910A Low Skew PLL Clock Driver Turboclock Jr.|
|5991A Programmable Skew PLL Clock Driver Turboclock|
|59920A Low Skew PLL Clock Driver Turboclock Jr.|
|5992A Programmable Skew PLL Clock Driver Turboclock|
|5T2010 2.5V Zero Delay PLL Clock Driver Teraclock|
|5T2110 2.5V Zero Delay PLL Differential Clock Driver Teraclock|
|5T905 2.5V Single Data Rate 1:5 Clock Buffer Terabuffer|
|5T9050 2.5V Single Data Rate 1:5 Clock Buffer Terabuffer Jr.|
|5T907 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer|
|5T9070 2.5V Single Data Rate 1:10 Clock Buffer Terabuffer Jr.|
|5T915 2.5V Differential 1:5 Clock Buffer Terabuffer|
|5T940 Precision Clock Generator|
|5T9820 2:10 Zero-delay Buffer With Single-ended Outputs NL68|
|5T9820NLI 2:10 Zero-delay Buffer|
|5T9821 2:6 Zero-delay Buffer With Complementary Outputs|
|5T9821NLI 2:6 Zero-delay Buffer w/ Complementary Outputs Lvttl, Hstl, Ehstl, Lvpecl Lvttl, Hstl, Ehstl 68-VFQFPN|
|5T9890 2:10 Programmable-skew Buffer With Single-ended Outputs|
|5T9890NLI 2:10 Programmable-skew Buffer Lvttl, Hstl, Ehstl, Lvpecl Lvttl, Hstl, Ehstl 68-VFQFPN|
|5T9891 2:6 Programmable-skew Buffer With Complementary Outputs|