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Part: 5V9955
Category:
Timing Circuits
-> Clock management
Description: 3.3V Programmable Skew Dual PLL Clock Driver Turboclock ii
Company: Integrated Device Technology, Inc.
Datasheet: Download 5V9955 datasheet File size : 3096 kB
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Datasheet text preview:
IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCKTM W
FEATURES:
· · · · · · · · · · · · · · · · ·
IDT5V9955 PRELIMINARY
Ref input is 5V tolerant 8 pairs of programmable skew outputs Two separate A and B banks for individual control Low skew: 185ps same pair, 250ps same bank, 350ps both banks Selectable positive or negative edge synchronization on each bank: excellent for DSP applications Synchronous output enable on each bank Input frequency: 2MHz to 200MHz Output frequency: 6MHz to 200MHz 3-level inputs for skew and PLL range control 3-level inputs for feedback divide selection multiply / divide ratios of (1-6, 8, 10, 12) / (2, 4) PLL bypass for DC testing External feedback, internal loop filter 12mA balanced drive outputs Low Jitter: <100ps cycle-to-cycle Power-down mode on each bank Lock indicator on each bank Available in BGA package
DESCRIPTION
The IDT5V9955 is a high fanout 3.3V PLL based clock driver intended for high performance computing and data-communications applications. A key feature of the programmable skew is the ability of outputs to lead or lag the REF input signal. The IDT5V9955 has sixteen programmable skew outputs in eight banks of 2. The two separate PLLs allow the user to independently control A and B banks. Skew is controlled by 3-level input signals that may be hard-wired to appropriate HIGH-MID-LOW levels. The feedback input allows divide-by-functionality from 1 to 12 through the use of the xDS[1:0] inputs. This provides the user with frequency multiplication from 1 to 12 without using divided outputs for feedback. When the xsOE pin is held low, all the xbank outputs are synchronously enabled. However, if xsOE is held high, all the xbank outputs except x2Q0 and x2Q1 are synchronously disabled. The xLOCK is high when the xbank PLL has achieved phase lock. Furthermore, when xPE is held high, all the outputs are synchronized with the positive edge of the REF clock input. When xPE is held low, all the xbank outputs are synchronized with the negative edge of REF. The IDT5V9955 has LVTTL outputs with 12mA balanced drive outputs.
FUNCTIONAL BLOCK DIAGRAM
ALOCK AFS APE REF APD
AsOE
T ES T
BPE
BFS
BLOCK
BP D BsOE
3 3 PLL /N 3 3 ADS1 :0 A1Q0 A1Q1 Skew S elect 3 A1F1 :0 3 B1F1 :0 3 BDS1:0 3 Skew Select AFB BF B 3 /N 3 3 PLL
3
B1Q0 B1Q1
A2Q0 A2Q1
Skew S elect
3 A2F1 :0 3 B2F1 :0
3 3
Skew Select
B2Q0 B2Q1
A3Q0 A3Q1
3 Skew S elect A3F1 :0 3 B3F1 :0
3 3
Skew Select
B3Q0 B3Q1
A4Q0 A4Q1
Skew S elect
3 A4F1 :0 3 B4F1 :0
3 3
Skew Select
B4Q0 B4Q1
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
c 2002 Integrated Device Technology, Inc.
JUNE 2002
1
DSC 5974/8
IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
6
A3Q1
A4Q0
A4Q1
APE
APD
A4F1
A3F1
AFS
B2F1
B1F1
BDS1
BLOCK
BVDDQ
B1Q0
B1Q1 BGND BGND BGND BGND B4Q0
R
B2Q0 B2Q1 BFB BGND B3Q0 B3Q1
T
5
A3Q0 AGND AFB A2Q1 A2Q0
A
AGND AGND AGND AGND A1Q1
B
AGND AGND AGND AGND A1Q0
C
AGND AVDDQ AVDDQ AVDDQ AVDDQ
D
ASOE AVDDQ AVDDQ ADS0 ALOCK
E
A4F0 AVDDQ AVDDQ A1F0 ADS1
F
A3F0 AVDDQ AVDDQ A2F0 A1F1
G
AVDD AVDDQ REF AGND A2F1
H
BGND TEST BVDDQ BVDD BFS
J
B2F0 BVDDQ BVDDQ B3F0 B3F1
K
B1F0 BVDDQ BVDDQ B4F0 B4F1
L
BDS0 BVDDQ BVDDQ BSOE BPD
M
BVDDQ BVDDQ BVDDQ BGND BPE
N
BGND BGND BGND BGND B4Q1
P
4
3
2
1
FPBGA TOP VIEW
96 BALL FPBGA PACKAGE ATTRIBUTES
1.5mm Max. 1.4mm Nom. 1.3mm Min.
0.8mm
6 5 4 3 2 1 A B C D E F G H J K L M N P R T
TOP VIEW
A 1 2 3
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
5.5mm 4 5 6
13.5mm
2
IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDDQ, VDD VI Description Supply Voltage to Ground DC Input Voltage REF Input Voltage Maximum Power Dissipation TSTG TA = 85°C TA = 55°C Max 0.5 to +4.6 0.5 to VDD+0.5 0.5 to +5.5 1.1 1.9 65 to +150 °C Unit V V V W
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter CI N Description Input Capacitance REF Others Typ. 8 5 Max. 10 7 Unit pF
NOTE: 1 . Capacitance applies to all inputs except TEST, xFS, xnF[1:0], and xDS[1:0].
Storage Temperature Range
NOTE: 1 . Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolutemaximum-rated conditions for extended periods may affect device reliability.
PIN DESCRIPTION
Pin Name REF xFB TEST (1) xsOE(1) Type IN IN IN IN Description Reference Clock Input Individual Feedback Inputs for A and B banks When MID or HIGH, disables PLL for A and B banks (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control Summary Table) remain in effect. Set LOW for normal operation. Individual Synchronous Output Enable for A and B banks. When HIGH, it stops clock outputs (except x2Q0 and x2Q1) in a LOW state (for xPE = H) - x2Q0 and x2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE is HIGH, the nF[1:0] pins act as output disable controls for individual banks when xnF[1:0] = LL. Set xsOE LOW for normal operation (has internal pull-down). Individual Selectable positive or negative edge control for A and B banks. When LOW/HIGH the outputs are synchronized with the negative/ positive edge of the reference clock (has internal pull-up). xnF[1:0] xFS xnQ[1:0] xDS [1:0] xPD xLOCK VDDQ VDD GND IN IN OUT IN IN OUT PWR PWR PWR 3-level inputs for selecting 1 of 9 skew taps or frequency functions Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.) Individual control on A and B banks. Eight banks of two outputs with programmable skew 3-level inputs for feedback divider selection for A and B banks Power down control. Shuts off either A or B bank of the chip when LOW (has internal pull-up). PLL lock indication signal for A and B banks. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the inputs. Power supply for output buffers Power supply for phase locked loop, lock output, and other internal circuitry Ground
xPE
IN
NOTE: 1 . When TEST = MID and xsOE = HIGH, PLL remains active with xnF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless xnF[1:0] = LL.
3
IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
PROGRAMMABLE SKEW
Output skew with respect to the REF input is adjustable to compensate for PCB trace delays, backplane propagation delays or to accommodate requirements for special timing relationships between clocked components. Skew is selectable as a multiple of a time unit (tU) which ranges from 625ps to 1.3ns (see Programmable Skew Range and Resolution Table). There are nine skew configurations available for each output pair. These configurations are chosen by the xnF1:0 control pins. In order to minimize the number of control pins, 3-level inputs (HIGH-MIDLOW) are used, they are intended for but not restricted to hard-wiring. Undriven 3-level inputs default to the MID level. Where programmable skew is not a requirement, the control pins can be left open for the zero skew default setting. The Control Summary Table shows how to select specific skew taps by using the xnF1:0 control pins.
EXTERNAL FEEDBACK
By providing two separate external feedbacks, the IDT5V9955 gives users flexibility with regard to skew adjustment. The xFB signal is compared with the input REF signal at the phase detector in order to drive the VCO. Phase differences cause the VCO of the PLL to adjust upwards or downwards accordingly. An internal loop filter moderates the response of the VCO to the phase detector. The loop filter transfer function has been chosen to provide minimal jitter (or frequency variation) while still providing accurate responses to input frequency changes.
PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
xFS = LOW Timing Unit Calculation (tU) VCO Frequency Range (FNOM)(1,2) Skew Adjustment Range(3) Max Adjustment: ±7.8125ns ±67.5° ±18.75% Example 1, FNOM = 25MHz Example 2, FNOM = 37.5MHz Example 3, FNOM = 50MHz Example 4, FNOM = 75MHz Example 5, FNOM = 100MHz Example 6, FNOM = 150MHz Example 7, FNOM = 200MHz tU = 1.25ns tU = 0.833ns tU = 0.625ns -- -- -- -- ±7.8125ns ±135° ±37.5% -- -- tU = 1.25ns tU = 0.833ns tU = 0.625ns -- -- ±7.8125ns ±270° ±75% -- -- -- -- tU = 1.25ns tU = 0.833ns tU = 0.625ns ns Phase Degrees % of Cycle Time 1/(32 x FNOM) 24 to 50MHz xFS = MID 1/(16 x FNOM) 48 to 100MHz xFS = HIGH 1/(8 x FNOM) 96 to 200MHz Comments
NOTES: 1 . The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. 2 . The level to be set on xFS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at x1Q1:0, x2Q1:0, and the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and xFB inputs will be FNOM when the output connected to xFB is undivided and xDS[1:0] = MM. The frequency of the REF and xFB inputs will be FNOM /2 or FNOM /4 when the part is configured for frequency multiplication by using a divided output as the xFB input and setting xDS[1:0] = MM. Using the xDS[1:0] inputs allows a different method for frequency multiplication (see Divide Selection Table). 3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed xQ output is used for feedback, then adjustment range will be greater. For example if a 4tU skewed output is used for feedback, all other outputs will be skewed 4tU in addition to whatever skew value is programmed for those outputs. `Max adjustment' range applies to output pairs 3 and 4 where ± 6tU skew adjustment is possible and at the lowest FNOM value.
4
IDT5V9955 3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W
INDUSTRIAL TEMPERATURE RANGE
DIVIDE SELECTION TABLE
xDS [1:0] LL LM LH ML MM MH HL HM HH xFB Divide-by-n 2 3 4 5 1 6 8 10 12 Permitted Output Divide-by-n connected to xFB(1) 1 or 2 1 1, 2, or 4 1 or 2 1, 2, or 4 1 or 2 1 or 2 1 1
NOTE: 1 . Permissible output division ratios connected to xFB. The frequency of the REF input will be FNOM/N when the part is configured for frequency multiplication by using an undivided output for xFB and setting xDS[1:0] to N (N = 1-6, 8, 10, 12).
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
nF1:0 LL (1) LM LH ML MM MH HL HM HH Skew (Pair #1, #2) 4tU 3tU 2tU 1tU Zero Skew 1tU 2tU 3tU 4tU Skew (Pair #3) Divide by 2 6tU 4tU 2tU Zero Skew 2tU 4tU 6tU Divide by 4 Skew (Pair #4) Divide by 2 6tU 4tU 2tU Zero Skew 2tU 4tU 6tU Inverted (2)
NOTES: 1 . LL disables outputs if TEST = MID and xsOE = HIGH. 2 . When pair #4 is set to HH (inverted), xsOE disables pair #4 HIGH when xPE = HIGH, xsOE disables pair #4 LOW when xPE = LOW.
RECOMMENDED OPERATING RANGE
Symbol VDD/VDDQ TA Description Power Supply Voltage Ambient Operating Temperature Min. 3 -40 Typ. 3.3 +25 Max. 3.6 +85 Unit V °C
5
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5V-1
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