Details, datasheet, quote on part number: 61298SA
CategoryMemory => SRAM => Async. SRAM
Description64K X 4 Static RAM
CompanyIntegrated Device Technology, Inc.
DatasheetDownload 61298SA datasheet


Features, Applications


x 4 high-speed static RAM Fast Output Enable (OE) pin available for added system flexibility High speed (equal access and cycle times) Commercial: 12/15 ns (max.) JEDEC standard pinout 300 mil 28-pin SOJ Produced with advanced CMOS technology Bidirectional data inputs and outputs Inputs/Outputs TTL-compatible Three-state outputs Military product compliant to MIL-STD-883, Class B CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective approach for memory intensive applications. The IDT61298SA features two memory control functions: Chip Select (CS) and Output Enable (OE). These two functions greatly enhance the IDT61298SA's overall flexibility in high-speed memory applications. Access times as fast as 12ns are available. The IDT61298SA offers a reduced power standby mode, ISB1, which enables the designer to considerably reduce device power requirements. This capability significantly decreases system power and cooling levels, while greatly enhancing system reliability. All inputs and outputs are TTL-compatible and the device operates from a single 5V supply. Fully static asynchronous circuitry, along with matching access and cycle times, favor the simplified system design approach. The IDT61298SA is packaged a 300 mil, 28-pin SOJ, providing improved board-level packing densities.


The a 262,144-bit high-speed static RAM organized It is fabricated using IDT's high-performance, high-reliability

Function Read Data Write Data Outputs Disabled Deselected - Standby (ISB) Deselecte d - Standby (ISB1)

NOTES: H = VIH, L = VIL, x = Don't care. 2. VLC = 0.2V, VHC = VCC -0.2V. 3. Other inputs VHC or VLC.

Rating Terminal Voltage with Respect to GND Operating Temperature Under Bias Storage Temperature Power Dissipation DC Output Current

Name WE OE GND VCC Description Addresses Data Input/Output Chip Select Write Enable Output Enable Ground Power

NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed + 0.5V.

Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions = 3dV VOUT = 3dV Max. 5 7 Unit pF

NOTE: 1. This parameter is determined by device characterization, but is not production tested.

Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. Typ. 5.0 0

NOTE: 1. VIL (min.) = 1.5V for pulse width less than 10ns, once per cycle.

61298SA12 Symbol ICC ISB ISB1 Parameter Dynamic Operating Current CS < VIL, Outputs Open, VCC = Max., = fMAX(2) Standby Power Supply Current (TTL Level) CS > VIH, VCC = Max., Outputs Open, = fMAX(2) Full Standby Power Supply Current (CMOS Level) CS > VHC, VCC = Max., = 0(2), VIN < VLC or VIN > VHC Com'l. 20 61298SA15 Com'l. 45 20 Unit mA

NOTES: 1. All values are maximum guaranteed values. 2. fMAX = 1/tRC (all address inputs are cycling at fMAX); = 0 means no address input lines are changing.

Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND 3ns 1.5V See Figures 1 and 2

Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ , tOHZ, tOW, tWHZ)


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