Details, datasheet, quote on part number: 6167SA
Part6167SA
CategoryMemory => SRAM => Async. SRAM
Description16K X 1 Static RAM
CompanyIntegrated Device Technology, Inc.
DatasheetDownload 6167SA datasheet
  

 

Features, Applications

Features

High-speed (equal access and cycle time) ­ Military: 25/35/45/55/70/85/100ns (max.) ­ Commercial: 15/20/25ns (max.) Low power consumption Battery backup operation 2V data retention voltage (IDT6167LA only) Available in 20-pin CERDIP and Plastic DIP, and 20-pin SOJ Produced with advanced CMOS high-performance technology CMOS process virtually eliminates alpha particle soft-error rates Separate data input and output Military product compliant to MIL-STD-883, Class B high reliability CMOS technology. Access times as fast as 15ns are available. The circuit also offers a reduced power standby mode. When CS goes HIGH, the circuit will automatically go to, and remain in, a standby mode as long as CS remains HIGH. This capability provides significant system-level power and cooling savings. The low-power (LA) version also offers a battery backup data retention capability where the circuit typically consumes only 1µW operating off a 2V battery. All inputs and the output of the IDT6167 are TTL-compatible and operate from a single 5V supply, thus simplifying system designs. The IDT6167 is packaged in a space-saving 20-pin, 300 mil Plastic DIP or CERDIP and a Plastic 20-pin providing high board-level packing densities. Military grade product is manufactured in compliance with the latest revision of MIL-STD-883, Class B, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.

Description

The a 16,384-bit high-speed static RAM organized x 1. The part is fabricated using IDT's high-performance,

Symbol VTERM Rating Terminal Voltage with Respect to GND Operating Temperature Under Bias Storage Temperature Power Dissipation DC Output Current Com'l. to +7.0 Mil. to +7.0 Unit V

NOTE: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Description Address Inputs Chip Select Write Enable Power DATAIN DATAOUT Ground

Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 7 Unit pF

NOTE: 1. This parameter is determined by device characterization, but is not production tested.
Mode Standby Read Write H L Output High-Z DATAOUT High-Z Power Standby Active
Symbol VCC GND VIH VIL Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min.
NOTE: 1. VIL (min.) = ­3.0V for pulse width less than 20ns, once per cycle.

6167SA/LA15 Symbol ICC1 Parameter Operating Power Supply Current CS < VIL, Outputs Open VCC = Max., = 0(3) Dynamic Operating Current CS < VIL, Outputs Open VCC = Max., = fMAX(3) Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open VCC = Max., = fMAX(3) Full Standby Power Supply Current (CMOS Level) CS > VHC, VCC = Max., VIN > VHC or VIN < VLC, = 0(3) Power SA LA Com'l. 6167SA/LA20 Com'l. 6167SA/LA25 Com'l. Mil.

6167SA/LA35(2) Symbol ICC1 Parameter Operating Power Supply Current CS < VIL, Outputs Open VCC = Max., = 0(3) Dynamic Operating Current CS < VIL, Outputs Open VCC = Max., = fMAX(3) Standby Power Supply Current (TTL Level) CS > VIH, Outputs Open VCC = Max., = fMAX(3) Full Standby Power Supply Current (CMOS Level) CS > VHC, VCC = Max., VIN > VHC or VIN < VLC, = 0(3) Power SA LA Mil. 6167SA/LA45(2) Mil. 6167SA/LA55(2) Mil. 6167SA/LA70(2) Mil.

NOTES: 1. All values are maximum guaranteed values. to +125°C temperature range only. Also available; 85ns and 100ns Military devices. 3. fMAX = 1/tRC, only address inputs cycling at fMAX. = 0 means no address inputs change.


 

Related products with the same datasheet
IDT6167SA100DB
IDT6167SA100LB
IDT6167SA15P
IDT6167SA15PB
IDT6167SA15Y
IDT6167SA15YB
IDT6167SA20DB
IDT6167SA20LB
IDT6167SA20P
IDT6167SA20PB
IDT6167SA20Y
IDT6167SA20YB
Some Part number from the same manufacture Integrated Device Technology, Inc.
6168LA 5V, 4k X 4, CMOS, Asynchronous, Static RAM
6168SA 5V, 4K X4, CMOS, Asynchronous, Static RAM
7005 8K X 8 Dual-port RAM
7006 16 K X 8 Dual-port RAM
7007 32K X 8 Dual-port RAM
7008 64K X 8 Dual-port RAM
7009 128K X 8 Dual-port RAM
70121 2K X 9 Dual-port RAM
70125
7014 4K X 9 Dual-port RAM
7015 8K X 9 Dual-port RAM
7016 16K X 9 Dual-port RAM
7018 64K x9 Dual-port RAM
7019 128K x9 Dual-port RAM
7024 4K X 16 Dual-port RAM
7025 8K X 16 Dual-port RAM
7026 16K X 16 Dual-port RAM
70261 16K X 16 Dual-port RAM W/int
7027 32K X 16 Dual-port RAM
7028 64K X16 Dual-port RAM
7034 4K X 18 Dual-port RAM
Same catergory

Am29LV008B : . 8 Megabit x 8-Bit) CMOS 3.0 Volt-only Boot Sector Flash Memory s Single power supply operation Full voltage range: to 3.6 volt read and write operations for battery-powered applications Regulated voltage range: to 3.6 volt read and write operations and for compatibility with high performance 3.3 volt microprocessors s Manufactured 0.32 µm process technology.

IDT72V36100 : 3.3v High-density Supersync(tm) ii 36-bit Fifo. Choose among the following memory organizations:Commercial 36 133 MHz operation (7.5 ns read/write cycle time) User selectable input and output port bus-sizing to x36 out to x18 out to x9 out to x36 out to x36 out Big-Endian/Little-Endian user selectable byte representation 5V input tolerant Fixed, low first word latency Zero latency retransmit Auto.

K3N6U1000C : 32M bit. = K3N6U1000C / K3N6V1000C 32M-Bit (4Mx8 / 2Mx16) CMOS Mask ROM ;; Organization = 4Mx8/2Mx16 ;; Voltage(V) = 3.0 ;; Speed(ns) = 100(50pF) ;; Package = 44SOP,44TSOP2,48TSOP1 ;; Current (mA/uA) = 50/50 ;; Production Status = Eol ;; Comments = -.

M16024EJ2V0DS00 : SRAM. The by 18-bit and the by 36-bit ZEROSB static RAM fabricated with advanced CMOS technology using full CMOS six-transistor memory cell. The µPD44321182 and µPD44321362 are optimized to eliminate dead cycles for read to write, or write to read transitions. These ZEROSB static RAMs integrate unique synchronous peripheral circuitry, 2-bit burst counter.

M50LPW040K : 4 Mbit 512kb X8, Uniform Block 3v Supply Low Pin Count Flash Memory. 4 Mbit (512Kb x8, Uniform Block) 3V Supply Low Pin Count Flash Memory SUPPLY VOLTAGE ­ VCC to 3.6V for Program, Erase and Read Operations ­ VPP = 12V for Fast Program and Fast Erase (optional) TWO INTERFACES ­ Low Pin Count (LPC) Standard Interface for embedded operation with PC Chipsets. ­ Address/Address Multiplexed (A/A Mux) Interface for programming.

M5M5V208 : 2097152-bit (262144-word BY 8-bit) CMOS SRAM. The is 2,097,152-bit CMOS static RAM organized by 8-bit which is fabricated using high-performance quadruple-polysilicon and double metal CMOS technology. The use of thin film transistor(TFT) load cells and CMOS periphery results in a high density and low power static RAM. The M5M5V208 is designed for memory applications where high reliability, large.

MR18R0824AM0 : Normal RIMM. = MR18R0824AM0 ;; Density(MB) = 64 ;; Organization = 32Mx18 ;; Component Composition = (8Mx18)x4 ;; Voltage(V) = 2.5 ;; Refresh = 18K/32ms ;; Speed(MHz)/ TRAC(ns) = 300/53.3,356/45,400/45 ;; #of Pin = 184 ;; Production Status = Eol ;; Comments = Ecc.

MSM514256C : DRAMs and ASMs. 256K X 4 DRAM FPM. The Ą 4-bit dynamic RAM fabricated in Oki's silicon-gate CMOS technology. The MSM514256C/CL achieves high integration, high-speed operation, and low-power consumption because Oki manufactures the device in a quadruple-layer polysilicon/single-layer metal CMOS process. The MSM514256C/CL is available a 20-pin plastic DIP, 26/20-pin plastic SOJ, or 20-pin.

MT36VDDT12872 : 184-Pin DDR Sdram Dimms, Registered, Ecc, Pll, (x72). 184-pin, dual in-line memory modules (DIMM) Fast data transfer rates; or PC2100 Utilizes 200 MT/s and 266 MT/s DDR SDRAM stacked components ECC, 1-bit error detection and correction Registered inputs with one-clock delay Phase-lock loop (PLL) clock driver to reduce loading 1GB (128 Meg 2GB (256 Meg x 72), and 4GB (128 Meg x 72) Vdd= VddQ = +2.5V Vddspd.

MX29F100B : Boot Sector Flash Memory. 5V±10% for read, erase and write operation 131072x8/ 65536x16 switchable Fast access time:55/70/90/120ns Low power consumption - 40mA maximum active - 1uA typical standby current Command register architecture - Byte/ Word Programming (7us/ 12us typical) - Erase 8K-Bytex2, 32K-Bytex1, and 64K-Byte x1) Auto Erase (chip) and Auto Program - Automatically.

PD488588 : 288m Bits Direct RAMbus DRAM. The Direct Rambus DRAM (Direct RDRAM) is a general purpose high-performance memory device suitable for use in a broad range of applications including computer memory, graphics, video, and any other application where high bandwidth and low latency are required. The is 288Mbits Direct Rambus DRAM (RDRAM), organized as 16M words by 18 bits. The use of Rambus.

TM248NBK36U-60 : ti TM248NBK36U, 1 048 576, 2 097 152 BY 36-Bit DRAM Module. Organization TM124MBK36F. TM248NBK36F. Single 5-V Power Supply (±10% Tolerance) 72-Pin Single-In-Line Memory Module (SIMM) for Use With Socket TM124MBK36F ­ Utilizes Two 16-Megabit and One 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ) Packages TM248NBK36F ­ Utilizes Four 16-Megabit and Two 4-Megabit DRAMs in Plastic Small-Outline J-Lead (SOJ).

W27L520W : 64KX8. The is a high speed, low power Electrically Erasable and Programmable Read Only Memory organized × 8 bits. It includes latches for the lower 8 address lines to multiplex with the 8 data lines. To cooperate with the MCU, this device could save the external TTL component, also cost and space. It requires only one supply in the range 3.0V in normal read.

WED3DG6464V : Density = 512MB ;; Organization = 64Mx64 ;; Components = 64Mx8 (8) Stack ;; Speed MHZ = 100-133 ;; Volt = 3.3 ;;.

KFN2G16Q2A : OneNAND™ 2G MuxOneNAND™ is a monolithic integrated circuit with a NAND Flash array using a NOR Flash interface. This device includes control logic, a NAND Flash array, and 5KB of internal BufferRAM. The BufferRAM reserves 1KB for boot code buffering (BootRAM) and 4KB for data buffering (DataRAM), split between 2 independent buffers. It has a x16 Host.

HXSR01608-EH : 2M X 8 STANDARD SRAM, CUUC3. s: Memory Category: SRAM Chip ; Density: 16777 kbits ; Number of Words: 2000 k ; Bits per Word: 8 bits ; Package Type: CERAMIC, DIE-3 ; Pins: 3 ; Logic Family: CMOS ; Supply Voltage: 1.8V ; Operating Temperature: -55 to 125 C (-67 to 257 F).

MT18VDDF12872DG-202XX : 128M X 72 DDR DRAM MODULE, 0.8 ns, DMA184. s: Memory Category: DRAM Chip ; Density: 9663676 kbits ; Number of Words: 128000 k ; Bits per Word: 72 bits ; Package Type: DIMM-184 ; Pins: 184 ; Logic Family: CMOS ; Supply Voltage: 2.5V ; Access Time: 0.8000 ns ; Operating Temperature: 0 to 70 C (32 to 158 F).

 
0-C     D-L     M-R     S-Z