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Part: 7008
Category:
Interface and Interconnect
-> Multi-Ports
Description: 64K X 8 Dual-port RAM
Company: Integrated Device Technology, Inc.
Datasheet: Download 7008 datasheet File size : 84 kB
Request For quote: Find where to buy 7008
Datasheet text preview:
HIGH-SPEED 64K x 8 DUAL-PORT STATIC RAM
Features
x x x
IDT7008S/L
x
x
True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access Military: 25/35/55ns (max.) Industrial: 55ns (max.) Commercial: 20/25/35/55ns (max.) Low-power operation IDT7008S Active: 750mW (typ.) Standby: 5mW (typ.) IDT7008L Active: 750mW (typ.) Standby: 1mW (typ.) Dual chip enables allow for depth expansion without external logic
x
x x x
x x x x
IDT7008 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (±10%) power supply Available in 84-pin PGA, 84-pin PLCC, and a 100-pin TQFP Industrial temperature range (40°C to +85°C) is available for selected speeds
Functional Block Diagram
R/WL CE0L CE1L OEL R/WR CE0 R CE1R OE R
I/O0-7L
I/O Control
I/O Control
I/O0-7R
BUSYL A15L A0L
(1,2)
BUSY R 64Kx8 MEMORY ARRAY 7008
16 16
(1,2)
Address Decoder
Address Decoder
A 15R A 0R
CE0L CE1L OEL R/W L SEML (2) INTL
ARBITRATION INTERRUPT SEMAPHORE LOGIC
CE0R CE1R OER R/WR SEM R (2) INT R
3198 drw 0 1
M/S
(1)
NOTES: 1 . BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH). 2 . BUSY and INT are non-tri-state totem-pole outputs (push-pull).
MAY 2000
DSC 3198/6
1
©2000 Integrated Device Technology, Inc.
IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Description
The IDT7008 is a high-speed 64K x 8 Dual-Port Static RAM. The IDT7008 is designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-or-more word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in full-speed, errorfree operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (CE0 and CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 750mW of power. The IDT7008 is packaged in a 84-pin Ceramic Pin Grid Array (PGA), a 84-pin Plastic Leadless Chip Carrier (PLCC) and a 100-pin Thin Quad Flatpack (TQFP).
Pin Configurations(1,2,3)
INDEX
A6R A5R A4R A3R A2R A1R A0R INTR BUSYR M/S GND BUSYL INTL NC A0L A1L A2L A3L A4L A5L A6L
11 10 9 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
A7R A8R A9R A10R A11R A12R A13R A14R A15R NC GND NC NC CE0R CE1R SEMR R/WR OER GND GND NC
87 65 43 2 1 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 IDT7008J J84-1(4) 84-Pin PLCC Top Vi ew(5) 55 31 54 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53
NC I/O7R I/O6R I/O5R I/O4R I/O3R Vcc I/O2R I/O1R I/O0R GND Vcc I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L ,
3198 drw 02
NOTES: 1 . This text does not indicate orientation of the actual part marking. 2 . All Vcc pins must be connected to power supply. 3 . Package body is approximately 1.15 in x 1.15 in x .17 in. 4 . This package code is used to reference the package diagram. 5 . All GND pins must be connected to ground supply.
A7L A8L A9L A10L A11L A12L A13L A14L A15L NC Vcc NC NC CE0L CE1L SEML RIWL OEL GND
2
GND NC
IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
Index
NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L NC Vcc NC NC NC NC CE0L CE1L SEML R/WL OEL GND NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68 67
NC NC A6L A5L A4L A3L A2L A1L A0L NC INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R NC NC
IDT7008PF PN100-1(4) 100-Pin TQFP Top View(5)
66 65 64 63 62 61 60 59 58 57 56 55 54 53
52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R NC GND NC NC NC NC CE0R CE1R SEMR R/WR OER GND GND NC ,
3198 drw 03
NOTES: 1 . This text does not indicate orientation of the actual part marking. 2 . All Vcc pins must be connected to power supply. 3 . Package body is approximately 14mm x 14mm x 1.4mm. 4 . This package code is used to reference the package diagram. 5 . All GND pins must be connected to ground supply.
GND NC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L Vcc GND I/O0R I/O1R I/O2R Vcc I/O3R I/O4R I/O5R I/O6R I/O7R NC NC NC
3 6.42
IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't)
63 61 60 58 55 54 51 48 46 45 42
11
66
A7R
64
A9R
A10R
62
A12R
59
A15R
56 49
NC
50
NC
SEMR
47
OER
44
GND
43 40
NC
10
67
A4R
65
A6R
A8R
A11R
A14R
57
CE1R
53
CE0R
52
R/WR
GND
41
NC
I/O6R
39
09
69
A3R
68
A5R
A13R
GND
NC
I/O7R
38
I/O5R
37
08
72
A1R
71
A2R
73 33
I/O4R
35
I/O3R
34
07
BUSYR
75
INTR
70
M/S
74
I/O0R IDT7008G G84-3(4) 84-Pin PGA Top View(5)
32
I/O2R
31
I/O1R
36
06 BUSYL
76
A0R
77
GND
78
GND
28 29
Vcc
30
Vcc
05 04
INTL
79 80
NC
A0L
GND
I/O1L
26
I/O0L
27
A1L
81 83
A2L
7 11 12
I/O3L
23
I/O2L
25
03
82
A3L
1
A5L
2 5 8
A13L
10
Vcc
14
NC
17 20
I/O6L
22
I/O4L
24
02
84
A4L
3
A7L
4
A8L
6
A11L
9
A14L
15
NC
CE0L
13
R/WL
16
GND
18
I/O7L
19
I/O5L
21
01
A6L A
A9L B
A10L C
A12L D
A15L E
CE1L F
NC G
SEML H
OEL J
GND K
NC L
,
3198 drw 04
INDEX
NOTES: 1 . All Vcc pins must be connected to power supply. 2 . All GND pins must be connected to ground supply. 3 . Package body is approximately 1.12 in x 1.12 in x .16 in. 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part marking.
Pin Names
Left Port C E0 L, CE1L R/WL OEL A0 L - A15L I/O0 L - I/O7L SEML INTL BUSYL Right Port C E0R, CE1R R/WR OER A0R - A15R I/O0R - I/O7R SEMR INTR BUSYR M/ S VCC GND Names Chip Enables Read/Write Enable Output Enable Add ress Data Input/Output Semaphore Enable Interrup t Flag Busy Flag Maste r or Slave Select Power Ground
3198 tbl 01
4
IDT7008S/L High-Speed 64K x 8 Dual-Port Static RAM
Military, Industrial and Commercial Temperature Ranges
Tr uth Table I: Chip Enable(1)
CE C E0 VIL L VCC -0.2V X CE1 VIH > VCC -0.2V X VIL X <0.2V Port Selected (TTL Active) Port Selected (CMOS Active) Port Deselected (TTL Inactive) Port Deselected (TTL Inactive) Port Deselected (CMOS Inactive) Port Deselected (CMOS Inactive)
3198 tbl 02
Mode
NOTES: 1 . Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only.
Truth Table II: Non-Contention Read/Write Control
Inputs(1) CE
(2)
Outputs SEM H H H X I/O0 -7 Hig h-Z DATA IN DATAOUT Hig h-Z Des elec ted : Power-Down Write to memory Read memory Outputs Disabled
3198 tbl 03
R/W X L H X
OE X X L H
Mode
H L L X
NOTES: 1 . A0L A15L A0R A15R. 2 . Refer to Chip Enable Truth Table.
Truth Table III: Semaphore Read/Write Control(1)
Inputs CE
(2)
Outputs SEM L L L I/O0 -7 DATAOUT DATAIN
______
R/W H
OE L X X
Mode Read Semaphore Flag Data Out Write I/O0 into Semaphore Flag Not Allowed
3198 tbl 04
H H L
X
NOTES: 1 . There are eight semaphore flags written to via I/O0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2. 2 . Refer to Chip Enable Truth Table.
5 6.42
Others parts begin by 70
70-1 70-2 70-3
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