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Part: 7009
Category:
Interface and Interconnect
-> Multi-Ports
Description: 128K X 8 Dual-port RAM
Company: Integrated Device Technology, Inc.
Datasheet: Download 7009 datasheet File size : 84 kB
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Datasheet text preview:
HIGH-SPEED 128K x 8 DUAL-PORT STATIC RAM
Features
x x x
IDT7009L
x
x
x
True Dual-Ported memory cells which allow simultaneous reads of the same memory location High-speed access Commercial: 15/20ns (max.) Low-power operation IDT7009L Active: 1W (typ.) Standby: 1mW (typ.) Dual chip enables allow for depth expansion without external logic IDT7009 easily expands data bus width to 16 bits or more using the Master/Slave select when cascading more than one device
x x x
x x x x
M/S = VIH for BUSY output flag on Master, M/S = VIL for BUSY input on Slave Interrupt Flag On-chip port arbitration logic Full on-chip hardware support of semaphore signaling between ports Fully asynchronous operation from either port TTL-compatible, single 5V (±10%) power supply Available in a 100-pin TQFP Industrial temperature range (40°C to +85°C) is available for selected speeds
Functional Block Diagram
R/WL CE0L CE1L OEL R/WR CE0R CE1R OE R
I/O0-7L
I/O Control
I/O Control
I/O0-7R
BUSYL A16L A0L
(1,2)
BUSYR 128Kx8 MEMORY ARRAY 7009
17 17
(1,2)
Address Decoder
Address Decoder
A16R A0R
CE0L CE1L OEL R/W L SEML (2) INTL
ARBITRATION INTERRUPT SEMAPHORE LOGIC
CE0R CE1R OER R/WR SEMR (2) INT R
4839 drw 01
M/S
(1)
NOTES: 1 . BUSY is an input as a Slave (M/S = VIL) and an output when it is a Master (M/S = VIH). 2 . BUSY and INT are non-tri-state totem-pole outputs (push-pull).
JANUARY 2001
DSC-4839/2
1
©2000 Integrated Device Technology, Inc.
IDT7009L High-Speed 128K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description
The IDT7009 is a high-speed 128K x 8 Dual-Port Static RAM. The IDT7009 is designed to be used as a stand-alone 1024K-bit Dual-Port RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-ormore word systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 16-bit or wider memory system applications results in fullspeed, error-free operation without the need for additional discrete logic. This device provides two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature controlled by the chip enables (CE0 and CE1) permit the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only1W of power. The IDT7009 is packaged in a 100-pin Thin Quad Flatpack (TQFP).
Pin Configurations(1,2,3)
Index
NC NC A7L A8L A9L A10L A11L A12L A13L A14L A15L A16L Vcc NC NC NC NC CE0L CE1L SEML R/WL OEL GND NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68 67
NC NC A6L A5L A4L A3L A2L A1L A0L NC INTL BUSYL GND M/S BUSYR INTR A0R A1R A2R A3R A4R A5R A6R NC NC
I DT7009PF PN100-1(4) 100-Pin TQFP Top View(5)
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC A7R A8R A9R A10R A11R A12R A13R A14R A15R A16R GND NC NC NC NC CE0R CE1R SEMR R/WR OER GND GND NC
4839 drw 02
NOTES: 1 . All Vcc pins must be connected to power supply. 2 . All GND pins must be connected to ground. 3 . Package body is approximately 14mm x 14mm x 1.4mm. 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part marking.
GND NC I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L Vcc GND I/O0R I/O1R I/O2R Vcc I/O3R I/O4R I/O5R I/O6R I/O7R NC NC NC
2
IDT7009L High-Speed 128K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port CE0 L, CE1L R/WL OEL A0 L - A16L I/O0 L - I/O7L SEML INTL BUSYL Right Port CE0R, CE1R R/WR OER A0R - A16R I/O0R - I/O7R SEMR INTR BUSYR M/ S VCC GND Names Chip Enables Read/Write Enable Output Enable Add ress Data Input/Output Semaphore Enable Interrup t Flag Busy Flag Maste r or Slave Select Power Ground
4839 tbl 01
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rating Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature DC Output Current Commercial & Industrial -0.5 to +7.0 Military -0.5 to +7.0 Unit V
Recommended DC Operating Conditions
Symbol VCC Parameter Supply Voltage Gro und Inp ut High Voltage Inp ut Low Voltage Min. 4.5 0 2.2 -0.5(1) Typ. 5.0 0
____
Max. 5.5 0 6.0(2) 0.8
Unit V V V V
4839 tbl 04
TBIAS TSTG IOUT
-55 to +125 -65 to +150 50
-65 to +135 -65 to +150 50
o
GND
C
VIH
o
C
VIL
____
mA
4839 tbl 02
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to Vcc + 10%.
NOTES: 1 . VIL > -1.5V for pulse width less than 10ns. 2 . VTERM must not exceed Vcc + 10%.
Capacitance
S ym b o l C IN
(TA = +25°C, f = 1.0MHz) (TQFP Only)
P ar a m e te r (1) In p u t Cap a c i ta n c e O u tp u t Cap a c i ta n c e C o n d i ti o n s (2) V IN = 3d V V O UT = 3d V M a x. 9 10 Uni t pF pF
4839 tbl 05
Maximum Operating Temperature and Supply Voltage(1)
Grade Military Com mercial Ind ustrial Ambient Temperature(2) -55 C to +125 C 0 C to +70 C -40OC to +85OC
O O O O
COUT
GND 0V 0V 0V
Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10%
4839 tbl 03
NOTES: 1 . This parameter is determined by device characterization but is not production tested. 2 . 3dV represents the interpolated capacitance when the input and output signals switch from 0V to 3V or from 3V to 0V.
NOTES: 1 . Industrial Temperature: for specific speeds, packages and powers contact your sales office. 2. This is the parameter TA. This is the "instant on" case temperature.
3 6.42
IDT7009L High-Speed 128K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Tr uth Table I: Chip Enable(1,2)
CE C E0 VI L L VCC -0.2V X CE1 VIH > VCC -0.2V X VIL X <0.2V Port Selected (TTL Active) Port Selected (CMOS Active) Port Deselected (TTL Inactive) Port Deselected (TTL Inactive) Port Deselected (CMOS Inactive) Port Deselected (CMOS Inactive)
4839 tbl 06
Mode
NOTES: 1 . Chip Enable references are shown above with the actual CE0 and CE1 levels, CE is a reference only. 2 . 'H' = VIH and 'L' = VIL. 3 . CMOS standby requires 'X' to be either VCC - 0.2V.
Truth Table II: Non-Contention Read/Write Control
Inputs(1) CE
(2)
Outputs SEM H H H X I/O0 -7 Hig h-Z DATAIN DATA OUT Hig h-Z Des elec te d: Power-Down Write to memory Read memory Outputs Disabled
4 839 drw 07
R/W X L H X
OE X X L H
Mode
H L L X
NOTES: 1 . A0L A16L A0R A16R. 2 . Refer to Chip Enable Truth Table.
Truth Table III: Semaphore Read/Write Control(1)
I nputs CE
(2)
Outputs SEM L L L I / O 0 -7 DATA O U T DATA IN
______
R/ W H
OE L X X
Mode Re ad Semaphore Flag Data Out Write I/O0 into Semaphore Flag No t Allowed
4839 tbl 08
H H L
X
NOTES: 1 . There are eight semaphore flags written to via I/O0 and read from all the I/Os (I/O0-I/O7). These eight semaphore flags are addressed by A0-A2. 2 . Refer to Chip Enable Truth Table.
4
IDT7009L High-Speed 128K x 8 Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temper ature and Supply Voltage Range(2) (VCC = 5.0V ± 10%)
7009L Symbol |ILI| |ILO | VOL VOH Param eter Input Leakage Current
(1)
Test Conditions VCC = 5.5V, VIN = 0V to VCC C E = VIH, VOUT = 0V to VCC IOL = 4mA IOH = -4mA
Min.
___
Max. 5 5 0.4
___
Unit µA µA V V
4839 tbl 09
Output Leakage Current Output Low Voltage Output High Voltage
___
___
2.4
NOTES: 1. At Vcc < 2.0V, input leakages are undefined. 2 . Refer to Chip Enable Truth Table.
DC Electrical Characteristics Over the Operating Temper ature and Supply Voltage Range(1,6,7) (VCC = 5.0V ± 10%)
Symbol ICC Param eter Dynamic Operating Current (Both Ports Active) Standb y Current (Bo th Ports - TTL Level Inputs ) Standb y Current (One Port - TTL Level Inputs ) Full Standby Current (Bo th Ports - All CMOS Le ve l Inputs) Full Standby Current (One Port - All CMOS Level Inputs) Test Condition C E = VIL, Outputs Disabled SEM = VIH f = fMAX(2) C EL = CER = VIH SEMR = SEML = VIH f = fMAX(2) C E"A " = VIL and CE"B" = VIH(4) Activ e Port Outputs Disabled, f= fMAX(2) , SEMR = SEML = VIH Both Ports CEL and C ER > VCC - 0.2V, VIN > VCC - 0.2V o r VIN VCC - 0.2V C E"A " VCC - 0.2V(4) , SEMR = SEML > VCC - 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, Activ e Port Outputs Disabled , f = fMAX(2) Version COM'L IND COM'L IND COM'L IND COM'L IND COM'L IND L L L L L L L L L L 7009L15 Com 'l Only Typ. (1) Max 220
____
7009L20 Com 'l Only Typ.(1) Max 200
____
Unit mA
340
____
300
____
ISB 1
65
____
100
____
50
____
75
____
mA
ISB 2
145
____
225
____
130
____
195
____
mA
ISB 3
0.2
____
3.0
____
0.2
____
3.0
____
mA
ISB 4
135
____
220
____
120
____
190
____
mA
NOTES: 1 . VCC = 5V, TA = +25°C, and are not production tested. ICCDC = 120mA (Typ.) 2 . At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using "AC Test Conditions" of input levels of GND to 3V. 3 . f = 0 means no address or control lines change. 4 . Port "A" may be either left or right port. Port "B" is the opposite from port "A". 5 . Refer to Chip Enable Truth Table. 6 . Industrial Temperature: for specific speeds, packages and powers contact your sales office.
4839 tbl 10
5 6.42
Others parts begin by 70
70-1 70-2 70-3
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