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Part: 70V7599
Category:
Interface and Interconnect
-> Multi-Ports
Description: 128K X 36 Synchronous Bank-switchable Dual-port SRAM
Company: Integrated Device Technology, Inc.
Datasheet: Download 70V7599 datasheet File size : 115 kB
Request For quote: Find where to buy 70V7599
Datasheet text preview:
HIGH-SPEED 3.3V 128K x 36 SYNCHRONOUS BANK-SWITCHABLE DUAL-PORT STATIC RAM WITH 3.3V OR 2.5V INTERFACE
Features:
x
IDT70V7599S
x x
x x x
x
128K x 36 Synchronous Bank-Switchable Dual-ported SRAM Architecture 64 independent 2K x 36 banks 4 megabits of memory on chip Bank access controlled via bank address pins High-speed data access Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/ 4.2ns (133MHz) (max.) Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.) Selectable Pipelined or Flow-Through output mode Counter enable and repeat features Dual chip enables allow for depth expansion without additional logic Full synchronous operation on both ports 5ns cycle time, 200MHz operation (14Gbps bandwidth) Fast 3.4ns clock to data out
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x
x
x
x
x
1.5ns setup to clock and 0.5ns hold on all control, data, and address inputs @ 200MHz Data input, address, byte enable and control registers Self-timed write allows fast cycle time Separate byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, 3.3V (±150mV) power supply for core LVTTL compatible, selectable 3.3V (±150mV) or 2.5V (±100mV) power supply for I/Os and control signals on each port Industrial temperature range (-40°C to +85°C) is available at 166MHz and 133MHz Available in a 208-pin Plastic Quad Flatpack (PQFP), 208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball Grid Array (BGA) Supports JTAG features compliant with IEEE 1149.1
Functional Block Diagram
PL/FTL OPTL CLKL ADSL CNTENL REPEATL R/WL CE0L CE1L BE3L BE2L BE1L BE0L OEL PL/FTR OPTR CLKR ADSR CNTENR REPEATR R/WR CE0 R CE1 R BE3R BE2R BE1R BE0R OER
CONTROL LOGIC
MUX 2Kx36 MEMORY ARRAY (BANK 0) MUX
CONTROL LOGIC
I/O0L -35L
I/O CONTROL
MUX 2Kx36 MEMORY ARRAY (BANK 1) MUX
I/O CONTROL
I/O0 R-35R
A10L A0L BA5L BA4L BA3L BA2L BA1L BA0L
ADDRESS DECODE
ADDRESS DECODE
A10 R A0R BA5R BA4R BA3R BA2R BA1R BA0R
BANK DECODE MUX 2Kx36 MEMORY ARRAY (BANK 63)
BANK DECODE
NOTE: 1 . The Bank-Switchable dual-port uses a true SRAM core instead of the traditional dual-port SRAM core. As a result, it has unique operating characteristics. Please refer to the functional description on page 19 for details.
MUX , TDI TDO JTAG TMS TCK TRST
5626 drw 01
DECEMBER 2002
1
DSC 5626/4
©2002 Integrated Device Technology, Inc.
IDT70V7599S High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V7599 is a high-speed 128Kx36 (4Mbit) synchronous Bank-Switchable Dual-Ported SRAM organized into 64 independent 2Kx36 banks. The device has two independent ports with separate control, address, and I/O pins for each port, allowing each port to access any 2Kx36 memory block not already accessed by the other port. Accesses by the ports into specific banks are controlled via the bank address pins under the user's direct control. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V7599 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. The dual chip enables also facilitate depth expansion. The 70V7599 can support an operating voltage of either 3.3V or 2.5V on one or both ports, controllable by the OPT pins. The power supply for the core of the device(VDD) remains at 3.3V. Please refer also to the functional description on page 19.
Pin Configuration(1,2,3,4)
1 1 /0 8 /0 1 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17
IO19L IO18L
B1 B2
VSS
B3
TDO
B4
NC
B5
BA5L
B6
BA1L
B7
A8L
B8
BE1L
B9
VDD
B10
CLKL C NTE NL A4L
B11 B 12 B13
A0L
B14
OPTL I/O17L
B15 B16
VSS
B17
I/O20R
C1
VSS
C2
I/O18R
C3
TDI
C4
NC
C5
BA2L
C6
A9L
C7
BE2L
C8
CE0L
C9
VSS
C10
ADSL
C11
A5L
C 12
A1L
C13
VSS
C14
VDDQR I/O16L I/O15R
C15 C16 C17
VDDQL I/O19R VDD QR P L/F TL
D1 D2 D3 D4
NC
D5
BA3L
D6
A10L
D7
BE3L
D8
CE1L
D9
VSS
D10
R/WL
D11
A6L
D 12
A2L
D13
VDD
D14
I/O16R I/O15L
D15 D16
VSS
D17
I/O22L
E1
VSS
E2
I/O21L I/O20L BA4L
E3 E4
BA0L
A7L
BE0L
VD D
OEL REPEATL
A3L
VDD I/O17R VD DQL I/O14L I/O14R
E14 E15 E16 E 17
I/O23L I/O22R VDD QR I/O21R
F1 F2 F3 F4
I/O12L I/O13R
F14 F15
VSS
F16
I/O13L
F1 7
VDDQL I/O23R I/O24L
G1 G2 G3
VSS
G4
VSS
G14
I/O12R I/O11L VDDQR
G15 G16 G 17
I/O26L
H1
VSS
H2
I/O25L I/O24R
H3 H4
I/O9L VDD QL I/O10L I/O11 R
VDD
J1
I/O26R VDDQR I/O25R
J2 J3 J4
70V7599BF BF-208(5) 208-Pin fpBGA Top View(6)
H14
H15
H 16
H 17
VDD
J14
IO9R
J15
VSS
J16
I/O10R
J17
VDDQL
K1
VDD
K2
VSS
K3
VSS
K4
VSS
K14
VDD
K15
VSS
K16
VDDQR
K17
I/O28R
L1
VSS
L2
I/O27R
L3
VSS
L4
I/O7R VDDQL I/O8R
L14 L15 L16
VSS
L17
I/O29R I/O2 8L VDDQR I/O27L
M1 M2 M3 M4
I/O6R
M14
I/O7L
M15
VSS
M16
I/O8L
M 17
VDDQL I/O2 9L I/O30R
N1 N2 N3
VSS
N4
VSS
N14
I/O6L I/O5R VDDQR
N15 N 16 N 17
I/O31L
P1
VSS
P2
I/O31R I/O30L
P3 P4 P5 P6 P7 P8 P9 P10 P11 P12 P13
I/O3R VD DQL I/O4R
P14 P15 P16
I/O5L
P17
I/O32R I/O32L VDDQR I/O35R TRST BA5R BA1R
R1 R2 R3 R4 R5 R6 R7
A8R
R8
BE1R
R9
VDD
R10
CLKR CN TENR A4R
R11 R12 R13
I/O2L
R14
I/O3L
R15
VSS
R16
I/O4L
R 17
VSS
T1
I/O33L I/O34R T CK
T2 T3 T4
NC
T5
BA2R
T6
A9R
T7
BE2R CE0R
T8 T9
VS S
T10
ADSR
T11
A5R
T1 2
A1R
T13
VSS
T14
VDDQL I/O1R VDDQR
T15 T1 6 T1 7
I/O33R I/O3 4L VDDQL TMS
U1 U2 U3 U4
NC
U5
BA3R
U6
A10R
U7
BE3R
U8
CE1R
U9
VSS
U10
R/WR
A6R
U12
A2R
U13
VSS
U14
I/O0R
U15
VSS
U16
I/O2R
U17
VSS
I/O35L P L/FT R
NC
BA4R BA0R
A7R
BE0R
VDD
OER
A3R
A0R
VDD
OPTR I/O0L
I/O1L
,
NOTES: 1 . All VDD pins must be connected to 3.3V power supply. 2 . All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3 . All VSS pins must be connected to ground supply. 4 . Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch. 5 . This package code is used to reference the package diagram. 6 . This text does not indicate orientation of the actual part-marking.
5626 d rw 02c
6.42 2
IDT70V7599S High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration(1,2,3,4) (con't.)
70V7599BC BC-256(5) 256-Pin BGA Top View(6)
11/08/01 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A 15 A16
NC
B1
TDI
B2
NC
B3
NC
B4
BA3L
B5
BA0L
B6
A8L
B7
BE2L
B8
CE1L
B9
OEL CNTE NL
B10 B11
A5L
B12
A2L
B13
A0L
B14
NC
B 15
NC
B16
I/O18L
C1
NC
C2
TDO
C3
NC
C4
BA4L
C5
BA1L
C6
A9L
C7
BE3L
C8
CE0L R/WL REPEATL
C9 C10 C11
A4L
C12
A1L
C13
VDD
C14
I/O17L
C15
NC
C16
I/O18R I/O19L
D1 D2
VSS
D3
BA5L
D4
BA2L
D5
A10L
D6
A7L
D7
BE1L
D8
BE0L CLKL ADSL
D9 D10 D11
A6L
D12
A3L
D13
OPTL I/O17R I/O16L
D14 D15 D16
I/O20R I/O19R I/O20L PL/FTL VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDD
E1 E2 E3 E4 E5 E6 E7 E8 E9 E 10 E 11 E12 E13
I/O15R I/O15L I/O16R
E14 E 15 E16
I/O21R I/O21L I/O22L VDDQL
F1 F2 F3 F4
VDD
F5
VDD
F6
VSS
F7
VSS
F8
VSS
F9
VS S
F10
VDD
F11
VDD VDDQR I/O13L I/O14L I/O14R
F12 F13 F14 F15 F16
I/O23L I/O22R I/O23R VDDQL
G1 G2 G3 G4
VDD
G5
VSS
G6
VSS
G7
VSS
G8
VSS
G9
VSS
G10
VS S
G11
VDD VDDQR I/O12R I/O13R I/O12L
G12 G13 G14 G15 G16
I/O24R I/O24L I/O25L VDDQR
H1 H2 H3 H4
VSS
H5
VSS
H6
VSS
H7
VSS
H8
VSS
H9
VSS
H10
VS S
H11
VSS
H12
VDDQL I/O10L I/O11L I/O11R
H13 H14 H15 H16
I/O26L I/O25R I/O26R VDDQR VSS
J1 J2 J3 J4 J5
VSS
J6
VSS
J7
VSS
J8
VSS
J9
VSS
J10
VSS
J11
VSS
J12
VDDQL I/O9R
J13 J14
IO9L I/O10R
J15 J16
I/O27L I/O28R I/O27R VDDQL
K1 K2 K3 K4
VSS
K5
VS S
K6
VSS
K7
VSS
K8
VSS
K9
VSS
K10
VSS
K11
VSS
K12
VDDQR I/O8R I/O7R
K 13 K14 K 15
I/O8L
K16
I/O29R I/O29L I/O28L VDDQL
L1 L2 L3 L4
VSS
L5
VS S
L6
VSS
L7
VSS
L8
VSS
L9
VSS
L10
VS S
L11
VSS
L12
VDDQR I/O6R
L13 L14
I/O6L
L15
I/O7L
L16
I/O30L I/O31R I/O30R VDDQR
M1 M2 M3 M4
VDD
M5
VSS
M6
VSS
M7
VSS
M8
VSS
M9
VSS
M 10
VSS
M11
VDD
M12
VDDQL I/O5L
M13 M14
I/O4R I/O5R
M 15 M 16
I/O32R I/O32L I/O31L VDDQR
N1 N2 N3 N4
VDD
N5
VDD
N6
VSS
N7
VSS
N8
VSS
N9
VSS
N10
VDD
N11
VDD
N12
VDDQL I/O3R
N13 N14
I/O3L
N15
I/O4L
N16
I/O33L I/O34R I/O33R PL/FTR VDDQR VDDQR VDDQL VDDQL VDDQR VDDQR VDDQL VDDQL
P1 P2 P3 P4 P5 P6 P7 P8 P9 P10 P11 P12
VDD
P 13
I/O2L
P14
I/O1R I/O2R
P 15 P 16
I/O35R I/O34L TMS
R1 R2 R3
BA5R BA2R
R4 R5
A10R
R6
A7R
R7
BE1R BE0R CLKR ADSR
R8 R9 R10 R11
A6R
R12
A3R
R13
I/O0L I/O0R
R14 R15
I/O1L
R16
I/O35L
T1
NC
T2
TRST
T3
NC
T4
BA4R BA1R
T5 T6
A9R
T7
BE3R CE0R R/WR REPEATR
T8 T9 T10 T11
A4R
T12
A1R
T13
OPTR
T14
NC
T1 5
NC
T16
,
NC
TCK
NC
NC
BA3R BA0R
A8R
BE2R
CE1R
OER CNTE NR
A5R
A2R
A0R
NC
NC
NOTES: 5626 drw 02d 1 . All VDD pins must be connected to 3.3V power supply. 2 . All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3 . All VSS pins must be connected to ground supply. 4 . Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch. 5 . This package code is used to reference the package diagram. 6 . This text does not indicate orientation of the actual part-marking.
,
6.42 3
IDT70V7599S High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Configuration
1 1/0 8 /01
(1 ,2 ,3 ,4 )
(con't.)
208 207 206 205 204 203 202 201 200 199 198 197 196 195 194 193 192 191 190 189 188 187 186 185 184 183 182 181 180 179 178 177 176 175 174 173 172 171 170 169 168 167 166 165 164 163 162 161 160 159 158 157
VSS VDDQ R I/O18R I/O18L VSS PL/FTL TDI TDO NC NC NC BA5L BA4L BA3L BA2L BA1L BA0L A10L A9L A8L A7L BE3L BE2L BE1L BE0L CE1L CE0L VDD VDD VSS VSS CLKL OEL R/WL ADSL CNTENL REPEATL A6L A5L A4L A3L A2L A1L A0L VDD VDD VSS OPTL I/O17L I/O17R VDDQ R VSS
53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
I/O19L I/O19R I/O20L I/O20R VDDQL VSS I/O21L I/O21R I/O22L I/O22R VDDQR VSS I/O23L I/O23R I/O24L I/O24R VDDQL VSS I/O25L I/O25R I/O26L I/O26R VDDQR VSS VDD VDD VSS VSS VDDQL VSS I/O27R I/O27L I/O28R I/O28L VDDQR VSS I/O29R I/O29L I/O30R I/O30L VDDQL VSS I/O31R I/O31L I/O32R I/O32L VDDQR VSS I/O33R I/O33L I/O34R I/O34L
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52
70V7599DR DR-208(5) 208-Pin PQFP Top View(6)
156 155 154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105
I/O16L I/O16R I/O15L I/O15R VSS VDDQL I/O14L I/O14R I/O13L I/O13R VSS VDDQR I/O12L I/O12R I/O11L I/O11R VSS VDDQL I/O10L I/O10R I/O9L I/O9R VSS VDDQR VDD VDD VSS VSS VSS VDDQL I/O8R I/O8L I/O7R I/O7L VSS VDDQR I/O6R I/O6L I/O5R I/O5L VSS VDDQL I/O4R I/O4L I/O3R I/O3L VSS VDDQR I/O2R I/O2L I/O1R I/O1L
,
NOTES: 1 . All VDD pins must be connected to 3.3V power supply. 2 . All VDDQ pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to VIH (3.3V), and 2.5V if OPT pin for that port is set to VIL (0V). 3 . All VSS pins must be connected to ground supply. 4 . Package body is approximately 28mm x 28mm x 3.5mm. 5 . This package code is used to reference the package diagram. 6 . This text does not indicate orientation of the actual part-marking.
VSS VDDQL I/O35R I/O35L PL/FTR TMS TCK TRST NC NC NC BA5R BA4R BA3R BA2R BA1R BA0R A10R A9R A8R A7R BE3R BE2R BE1R BE0R CE1R CE0R VDD VDD VSS VSS CLKR OER R/WR ADSR CNTENR REPEATR A6R A5R A4R A3R A2R A1R A0R VDD VSS VSS OPTR I/O0L I/O0R VDDQL VSS
5 626 d rw 0 2a
6.42 4
IDT70V7599S High-Speed 128K x 36 Synchronous Bank-Switchable Dual-Port Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port CE0 L, CE1L R/WL OEL BA0 L - BA5L A0 L - A10L I/ O0 L - I/O35L CLKL PL/ FTL ADSL CN TENL REPEATL BE0 L - BE3L VDDQ L OPTL V DD VS S TDI TDO TCK TMS TRST Right Port CE0R, CE1R R/WR OER BA0R - BA5R A0R - A10R I/ O0R - I/O35R CLKR PL/FTR ADSR CN TENR REPEATR BE0R - BE3R VDDQR OPTR Chip Enables Read /Write Enable Output Enable Bank Address (4) Ad dres s Data Input/Output Clo ck Pip eline/ Flow-Thro ug h Ad dres s Strobe Enable Co unte r Enable Co unte r Repeat(3) Byte Enables (9-bit bytes) Po we r (I/O Bus) (3.3V or 2.5V)(1) Op tio n for selecting VDDQX(1,2) Powe r (3.3V)(1) Gro und (0V) Tes t Data Input Tes t Data Output Te s t Logic Clock (10MHz) Tes t Mode Select Re se t (Initialize TAP Controller)
56 26 tbl 01
Names
NOTES: 1 . VDD, OPTX, and VDDQX must be set to appropriate operating levels prior to applying inputs on the I/Os and controls for that port. 2 . OPTX selects the operating voltage levels for the I/Os and controls on that port. If OPTX is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V levels and VDDQX must be supplied at 3.3V. If OPTX is set to VIL (0V), then that port's I/Os and address controls will operate at 2.5V levels and VDDQX must be supplied at 2.5V. The OPT pins are independent of one another--both ports can operate at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V. 3 . When REPEATX is asserted, the counter will reset to the last valid address loaded via ADSX. 4 . Accesses by the ports into specific banks are controlled by the bank address pins under the user's direct control: each port can access any bank of memory with the shared array that is not currently being accessed by the opposite port (i.e., BA0L - BA5L BA0R - BA5R). In the event that both ports try to access the same bank at the same time, neither access will be valid, and data at the two specific addresses targeted by the ports within that bank may be corrupted (in the case that either or both ports are writing) or may result in invalid output (in the case that both ports are trying to read).
6.42 5
Others parts begin by 70
70-1 70-2 70-3
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