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Part: 70V9159
Category:
Interface and Interconnect
-> Multi-Ports
Description: 8K X 9 Sync,3.3V Dual-port RAM, Pipelined/flow-through
Company: Integrated Device Technology, Inc.
Datasheet: Download 70V9159 datasheet File size : 115 kB
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Datasheet text preview:
PRELIMINARY
HIGH-SPEED 3.3V 16/8K X 9 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
.eatures:
x x x
IDT70V9169/59L
x
x
x x
True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial: 6.5/7.5/9ns (max.) Industrial: 7.5ns (max.) Low-power operation IDT70V916/59L/59L Active: 450mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic
x
x x
x
Full synchronous operation on both ports 3.5ns setup to clock and 0ns hold on all control, data, and address inputs Data input, address, and control registers Fast 6.5ns clock to data out in the Pipelined output mode Self-timed write allows fast cycle time 10ns cycle time, 100MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (±0.3V) power supply Industrial temperature range (40°C to +85°C) is available for 83 MHz Available in a 100-pin Thin Quad Flatpack (TQFP) and 100pin fine pitch Ball Grid Array (fpBGA) packages.
.unctional Block Diagram
R/WL OEL CE0L CE1L R/WR OER CE0R CE1R
1 0 0/1
1 0 0/1
FT/PIPEL
0/1
1
0
0
1
0/1
FT/PIPER
I/O0L - I/O8L
I/O0R - I/O8R I/O Control I/O Control
A13L(1) A0 L CLKL ADSL CNTENL CNTRSTL
NOTE: 1. A13 is a NC for IDT70V9159.
A13R(1) Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A0R CLKR ADSR CNTENR CNTRSTR
5655 drw 01
JULY 2002
1
©2002 Integrated Device Technology, Inc. DSC-5655/1
T: E .
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a C r V5 99 1
IDT70V9169/59L High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Description:
The IDT70V9169/59 is a high-speed 16/8K x 9 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V9169/59 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 450mW of power.
Pin Configurations(1,2,3,4)
06/21/02
Index
NC NC A7L A8L A9L A10L A11L A12L A13L(1) NC NC NC VDD NC NC NC NC CE0L CE1L CNTRSTL R/WL OEL FT/PIPEL NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 2 74 3 73 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68
NC NC A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL Vss Vss ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R NC
70V9169/59PF PN100-1(5) 100-Pin TQFP Top View(6)
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
NC NC A7R A8R A9R A10R A11R A12R A13R(1) NC NC NC Vss NC NC NC NC CE0R CE1R CNTRSTR R/WR OER FT/PIPER Vss NC
5655 drw 02
NOTES: 1. A13 is a NC for IDT70V9159. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 14mm x 14mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking.
Vss I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L Vss I/O1L I/O0L VDD Vss I/O0R I/O1R I/O2R VDD I/O3R I/O4R I/O5R I/O6R I/O7R I/O8R NC NC
.
6.42 2
IDT70V9169/59L High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Pin Configurations(cont'd)(1,2,3,4)
70V9169/59PF BF100(5) 100-Pin fpBGA Top View(6)
0 6 /2 1 /0 2 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10
A6 R
B1
A9R
B2
A 12 R
B3
NC
B4
VSS
B5
VSS
B6
NC
B7
R/WR
B8
V SS
B9
NC
B10
A4 R
C1
A5R
C2
A 8R
C3
A 10R
C4
NC
C5
NC
C6
NC
C7
OER
C8
NC
C9
I/O6R
C10
A 3R
D1
NC
D2
NC
D3
A7R
D4
NC
D5
CE0 R C E1 R P L/FTR I/O7R I/O3R
D6 D7 D8 D9 D10
A 0R
E1
CL KR
E2
A 1R
E3 CNTENR F3
A 2R
E4
A11R
E5
A 13R(1 ) CNTRSTR I/O8R
E6 E7 E8
I/O5R I/O1R
E9 E10
VSS
F1
A DSR
F2
A1L
F4
A D SL
F5
VSS
F6
I / O4 R
F7
I / O2 R
F8
I / O0 R
F9
VDD
F10
VSS
G1 CNTENL H1
CL KL
G2
A0L
G3
A 3L
G4
V DD
G5
VSS
G6
V DD
G7
I/O2L
G8
I / O1 L
G9
I/O0L
G10
NC
H2
A 5L
H3
A12L
H4 H5
NC
R /WL
H6
NC
H7
I/O4L
H8
V SS
H9
I / O3 L
H10
,
A2L
J1
A 4L
J2
A 9L
J3
A13L(1)
J4 J5
NC NC
K5
C E1L
J6 J7
NC O EL
K7
I/O7L
J8
I/O6L
J9
I / O5 L
J10
NC
K1
A7L
K2
A10L
K3
NC
K4
NC
K6
V SS
K8
CNTR ST L
VSS
K9
I/O8L
K10
A 6L
A 8L
A11 L
NC
V DD
VD D
CE 0L
PL/FTL N C
5 6 5 5 d rw 0 3
NOTES: 1. A13 is a NC for IDT70V9159. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking.
6.42 3
IDT70V9169/59L High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Pin Names
L eft Port C E0L, CE1L R/WL OEL A0L - A13L
(1)
R i g h t Port C E0R, CE1R R/WR OER A0R - A13R
(1)
N am es Chip Enables Re ad/Write Enable Outp ut Enable Ad dress Data Input/Output Clo ck Add ress Strobe Counte r Enable Counte r Reset Flo w-Thro ug h/Pipe line Po we r (3.3V) Gro und (0V)
5655 tbl 01
I/O0L - I/O8L CLKL AD SL CN TE NL C NTRSTL FT/PIPEL
I/O0R - I/O8R CLKR AD SR CN TE NR C NTRSTR FT/PIPER VDD VSS
NOTE: 1. A13 is a NC for IDT70V9159.
Tr uth Table IRead/Write and Enable Control(1,2,3)
OE X X X L H CLK X CE0 H X L L L CE1 X L H H H R/W X X L H X I/O0 -8 Hig h-Z Hig h-Z DATAIN DATAOUT Hig h-Z Mode De sele cted --Po wer Down De sele cted --Po wer Down Write Re ad Outputs Disabled
5655 tbl 02
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal.
6.42 4
IDT70V9169/59L High-Speed 3.3V 16/8K x 9 Dual-Port Synchronous Pipelined Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Tr uth Table IIAddress Counter Control(1,2)
E xtern al Add ress An X X X P revio us In ternal Add ress X An An + 1 X In ternal Add ress Used An An + 1 An + 1 A0 C LK ADS L(4 ) H H X CNTEN X L
(5 )
CNTRST H H H L
(4 )
I/O (3 ) DI/O (n) D I/O(n + 1 ) D I/O(n + 1 ) D I/O(0 ) E x te rn al Ad d re s s Used
M O DE
C o u nte r Enab le d -- In te rna l Ad d re s s g e n e rati o n E x te rn al Ad d re s s Blo c k e d -- C o u nte r disab le d (An + 1 re us e d ) C o u nte r Re s e t to Ad d re s s 0
5655 tbl 03
H X
NOTES: 1 . "H" = VIH, "L" = VIL, "X" = Don't Care. 2 . CE 0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3 . Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4 . ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB. 5 . The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
Recommended Operating Temperature and Supply Voltage
Grade Comm ercial Industrial Ambient Temperature(1) 0OC to +70OC -40 C to +85 C
O O
Recommended DC Operating Conditions
Symbol Parameter Sup ply Voltage Gro und Input High Voltage Input Low Voltage Min. 3. 0 0 2. 0 -0.3(1) Typ. 3. 3 0
____
Max. 3. 6 0 VDD+ 0.3V(2) 0. 8
Unit V V V V
56 55 tbl 05
GND 0V 0V
VDD 3.3V + 0.3V 3.3V + 0.3V
5655 tbl 04
VDD VSS VIH V IL
NOTES: 1 . This is the parameter TA. This is the "instant on" case temperature.
____
NOTES: 1 . VIL > -1.5V for pulse width less than 10 ns. 2 . VTERM must not exceed VDD+0.3V.
Absolute Maximum Ratings(1)
Symbol VTE RM
(2)
Capacitance(1)
Uni t V
Rating Terminal Voltage with Respect to GND Temp e rature Und e r Bias Sto rag e Temp e rature DC Output Current
Commerci al & Industrial -0.5 to +4.6
(TA = +25°C, f = 1.0MHZ)
Symbol CIN COUT
(3)
Parameter Inp ut Capacitance Outp ut Capacitance
Conditions(2) VIN = 3dV V OUT = 3dV
Max. 9 10
Unit pF pF
5655 tbl 07
TB IAS TS TG IO UT
-55 to +125 -65 to +150 50
o
C C
o
mA
5655 tbl 06 NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to VDD + 0.3V.
NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O.
6.42 5
Others parts begin by 70
70-1 70-2 70-3
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