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Part: 70V9269
Category:
Interface and Interconnect
-> Multi-Ports
Description: 16K X 16 Sync, 3.3V Dual-port RAM, Pipelined/flow-through
Company: Integrated Device Technology, Inc.
Datasheet: Download 70V9269 datasheet File size : 115 kB
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Datasheet text preview:
HIGH-SPEED 3.3V 16K x 16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Features:
x x
IDT70V9269S/L
x
x
x x
True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial: 9/12/15ns (max.) Low-power operation IDT70V9269S Active: 429mW (typ.) Standby: 3.3mW (typ.) IDT70V9269L Active: 429mW (typ.) Standby: 1.32mW (typ.) Flow-through or Pipelined output mode on either port via the FT/PIPE pin Counter enable and reset features Dual chip enables allow for depth expansion without
x
x
x x
x
additional logic Full synchronous operation on both ports 4ns setup to clock and 1ns hold on all Control, data, and address inputs Data input, address, and control registers Fast 9ns clock to data out in the Pipelined output mode Self-timed write allows fast cycle time 15ns cycle time, 66MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (±0.3V) power supply Industrial temperature range (40°C to +85°C) is available for selected speeds Available in a 128-pin Thin Quad Flatpack (TQFP) package
Functional Block Diagram
R/WL
UBL CE0L
1 0 0/1
R/WR
UBR CE0R
CE1L
LBL OEL
1 0 0/1
CE1R
LBR OER
FT/PIPEL
0/1
1b 0b
b
a
1a 0a
0a 1a
a
b
0b 1b
0/1
FT/PIPER
I/O8L-I/O15L I/O Control I/O0L-I/O7L I/O Control
I/O8R-I/O15R I/O0R-I/O7R
A13L A0L CLKL CNTENL
CNTRSTL ADSL
A13R Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg. A0R CLKR
ADSR CNTENR CNTRSTR
3752 drw 01
JANUARY 2001
1
©2000 Integrated Device Technology, Inc. DSC 3752/6
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V9269 is a high-speed 16K x 16 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address in-puts provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V9269 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 429mW of power.
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
A10R A11R A12R A13R N/C N/C N/C N/C LBR UB R CE 0R CE 1R CNTRST R V CC GN D R/WR OE R FT/ PIPER GN D I/O15R I/O14R I/O13R I/O12R V CC V CC I/O11R
Pin Configuration(1,2,3)
N/C N/C N/C N/C A9R A 8R A7R A6R A5R A4R A3R A2R A1R A0R NC CNTENR CLKR ADSR GND VC C ADSL CLKL CNTENL NC A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L N/C N/C N/C N/C
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
70V9269PRF PK-128(4) 128-Pin TQFP Top View(5)
A10L A11L A12L A13L N/C N/C N/C N/C L BL UBL CE 0L CE 1L CNTRST L V CC GND R/WL OE L FT /PIPEL GND I /O15L I /O14L I /O13L I /O12L V CC GND I /O11L
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
I/O10R I/O9R GND N/C I/O8R N/C N/C I/O7R VC C I/O6R I/O5R I/O4R GND I/O3R VC C I/O2R I/O1R I/O0R GND VC C I/O0L I/O1L GND I/O2L I/O3L GND I/O4L I/O5L I/O6L I/O7L VC C N/C N/C I/O8L N/C VCC I/O9L I/O10L
3752 drw 02
NOTES: 1 . All Vcc pins must be connected to power supply. 2 . All GND pins must be connected to ground supply. 3 . Package body is approximately 14mm x 20mm x 1.4mm. 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part-marking.
6.42 2
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port C E0L, CE1L R/WL OEL A0L - A13L I/O0L - I/O15L CLKL U BL LBL AD SL CNTENL C NTRSTL FT/PIPEL Right Port C E0R, CE1R R/WR OER A0R - A13R I/O0R - I/O15R CLKR U BR LBR AD SR CNTENR C NTRSTR FT/PIPER VCC GND Names Chip Enables Re ad /Write Enable Output Enable Addres s Data Input/Output Cloc k Up pe r Byte Select Lo we r Byte Select Addre ss Strobe Enable Counter Enable Counter Reset Flow-Throug h / Pipeline Power Ground
3752 tbl 01
Tr uth Table IRead/Write and Enable Control(1,2,3)
OE X X X X X X L L L H CLK CE0 H X L L L L L L L L CE1 X L H H H H H H H H UB X X H L H L L H L L LB X X H H L L H L L L R/W X X X L L L H H H X Upper Byte I/O8-1 5 Hig h-Z Hig h-Z Hig h-Z DATAIN Hig h-Z DATAIN DATAOUT Hig h-Z DATAOUT Hig h-Z Lower Byte I/O0 -7 Hig h-Z Hig h-Z Hig h-Z Hig h-Z DATAIN DATAIN Hig h-Z DATAOUT DATAOUT Hig h-Z De selectedPo wer Down De selectedPo wer Down Both Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Read Upper Byte Only Read Lower Byte Only Read Both Bytes Outputs Disabled
3752 tbl 02
MODE
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal.
6.42 3
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Tr uth Table IIAddress Counter Control(1,2)
Address X An An X Previous Address X X Ap Ap Addr Used 0 An Ap Ap + 1 CLK ADS X L(4) H H CN TEN X X H L
(5)
C NTRST L H H H
I/O(3) DI/ O(0) DI/ O(n) DI/ O(p) DI/ O(p+ 1)
MODE Counte r Reset to Address 0 Exte rnal Address Loaded into Counter Exte rnal Address Blocked--Counter disabled (Ap reused) Counte r Enabled--Internal Address generation
3752 tbl 03
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
Recommended Operating Temperature and Supply Voltage(1,2)
Grade Comme rcial Industrial Ambient Temperature 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 3.3V + 0.3V 3.3V + 0.3V
3752 tbl 04
Recommend DC Operating Conditions
Sym bol VCC GND VIH V IL Parameter Sup p ly Voltage Gro und Inp ut High Voltage Inp ut Low Voltage Mi n. 3.0 0 2.2 -0. 3
(1)
Typ. 3.3 0
____
Max. 3.6 0 VCC+0.3V 0.8
(2)
Uni t V V V V
3752 tbl 05
NOTE: 1 . Industrial temperature: for specific speeds, packages and powers contact your sales office. 2 . This is the parameter TA. This is the "instant on" case temperature.
____
NOTES: 1. VIL > -1.5V for pulse width less than 10 ns. 2 . VTERM must not exceed VCC + 0.3V.
Absolute Maximum Ratings(1)
Symbol VTE RM(2) Rating Te rminal Voltage with Respect to GND Te mpe rature Und er Bias Sto rag e Te mpe rature DC Output Current Commerci al & Industrial -0.5 to +4.6 Unit V
Capacitance(1) (TA = +25°C, f = 1.0MHz)
S ym b o l CIN COUT(3 ) Param eter Inp ut Capacitance Outp ut Capacitance Conditions(2 ) VIN = 3dV VO UT = 3dV Max. 9 10 Unit pF pF
3752 tbl 07
TBIAS TSTG IOUT
-55 to +125 -65 to +150 50
o
C C
o
mA
37 52 tbl 06
NOTES: 1 . These parameters are determined by device characterization, but are not production tested. 2 . 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3 . COUT also references CI/O.
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . VTERM must not exceed VCC + 0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to VCC + 0.3V.
6.42 4
IDT70V9269S/L High-Speed 16K x 16 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temper ature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V9269S Symbol |ILI| |ILO| VO L VOH Parameter Inp ut Leakage Current(1) Outp ut Leakage Current Outp ut Low Voltage Outp ut High Voltage Test Conditions V CC = 3.6V, VIN = 0V to VCC CE = VIH or CE1 = VIL, VOUT = 0V to VCC IOL = +4mA IOH = -4mA Min.
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70V9269L Min.
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Max. 10 10 0.4
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Max. 5 5 0.4
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Unit µA µA V V
3752 tbl 08
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2.4
2.4
NOTE: 1 . At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating Temper ture and Supply Voltage Range(3,6,7) (VCC = 3.3V ± 0.3V)
70V9269X9 Com'l Only Symbol ICC Parameter Dy nami c Op erating Current (Both Po rts Active) Standby Current (Both Po rts - TTL Lev el Inputs) Standby Current (One Po rt - TTL Lev el Inputs) Ful l Standby Current (Both Po rts - CMOS Lev el Inputs) Ful l Standby Current (One Po rt - CMOS Lev el Inputs) Test Condition CEL and CER= VIL, Outputs Disabled, f = fMAX(1) Version COM'L IND COM'L IND S L S L S L S L S L S L S L S L S L S L Typ. (4) 180 180
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70V9269X12 Com'l Only Typ.(4) 150 150
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70V9269X15 Com'l Only Typ.(4) 130 130
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Max. 260 225
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Max. 240 205
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Max. 220 185
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Unit mA
IS B1
CEL = CER = VIH f = fMAX
(1)
50 50
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75 65
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40 40
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65 50
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30 30
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55 35
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mA
IS B2
COM'L CE"A " = VIL and CE"B " = VIH(5) Ac tive Port Outputs Disabled, IND f=fMAX(1) Bo th Ports CEL and CER > VCC - 0.2V, VIN > VCC - 0.2V or VIN VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V, Active Port, Outputs Disable d, f = fMAX(1) COM'L IND COM'L IND
110 110
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170 150
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100 100
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160 140
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90 90
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150 130
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mA
IS B3
1.0 0.4
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5 3
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1.0 0.4
____ ____
5 3
____ ____
1.0 0.4
____ ____
5 3
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mA
IS B4
100 100
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160 140
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90 90
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150 130
____ ____
80 80
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140 120
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mA
NOTES: 1 . At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2 . f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3 . Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4 . Vcc = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ). 5 . CE X = VIL means CE0X = VIL and CE1X = VIH CE X = VIH means CE0X = VIH or CE1X = VIL CE X VCC - 0.2V CE X > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V 'X' represents "L" for left port or "R" for right port. 6 . 'X' in part number indicates power rating (S or L). 7 . Industrial temperature: for specific speeds, packages and powers contact your sales office.
3752 tbl 09
6.42 5
Others parts begin by 70
70-1 70-2 70-3
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