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Part: 70V9349
Category:
Interface and Interconnect
-> Multi-Ports
Description: 4K X 18 Sync, 3.3V Dual-port RAM, Pipelined/flow-through
Company: Integrated Device Technology, Inc.
Datasheet: Download 70V9349 datasheet File size : 115 kB
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Datasheet text preview:
PRELIMINARY
HIGH-SPEED 3.3V 8/4K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
.eatures:
x x x
IDT70V9359/49L
x
x
x x
True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial: 6.5/7.5/9ns (max.) Industrial: 7.5ns (max.) Low-power operation IDT70V9359/49L Active: 450mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic
x
x x
x
Full synchronous operation on both ports 3.5ns setup to clock and 0ns hold on all control, data, and address inputs Data input, address, and control registers Fast 6.5ns clock to data out in the Pipelined output mode Self-timed write allows fast cycle time 10ns cycle time, 100MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (±0.3V) power supply Industrial temperature range (40°C to +85°C) is available for 83 MHz Available in a 100-pin Thin Quad Flatpack (TQFP) and 100pin Fine Pitch Ball Grid Array (fpBGA) packages.
.unctional Block Diagram
R/WL
UBL CE0L
R/WR
UBR CE0R
CE1L
LBL OEL
1 0 0/1
1 0 0/1
CE1R
LBR OER
FT/PIPEL
0/1
1b 0b
b a 1a 0a
0a 1a
a
b
0b 1b
0/1
FT/PIPER
I/O9L-I/O17L I/O0L-I/O8L
I/O Control
I/O9R-I/O17R I/O Control I/O0R-I/O8R
A12L (1) A0L CLKL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg.
A12R(1) A0R CLKR
ADSL CNTENL CNTRSTL
ADSR CNTENR CNTRSTR
5638 drw 01
NOTE: 1. A12 is a NC for IDT70V9349.
JULY 2002
1
©2002 Integrated Device Technology, Inc. DSC-5638/2
IDT70V9359/49L High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Description:
The IDT70V9359/49 is a high-speed 8/4K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V9359/49 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 450mW of power.
Pin Configurations(1,2,3,4)
07/03/02
Index
A9L A10L A11L A12L(1) NC NC NC LBL UBL CE0L CE1L CNTRSTL R/WL OEL VDD FT/PIPEL I/O17L I/O16L VSS I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 2 74 3 73 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68
A 8L A 7L A 6L A 5L A 4L A 3L A 2L A 1L A 0L C N TE N L C LK L AD S L VS S V ss A D SR C L KR C NT E N R A 0R A 1R A 2R A 3R A 4R A 5R A 6R A 7R
70V9359/49PF PN100-1(5) 100-Pin TQFP Top View(6)
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A8R A9R A10R A11R A12R(1) NC NC NC LBR UBR CE0R CE1R CNTRSTR R/WR VSS OER FT/PIPER I/O17R VSS I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R .
5638 drw 02
NOTES: 1. A12 is a NC for IDT70V9349. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 14mm x 14mm x 1.4mm. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking.
I / O9 L I / O8 L V DD I /O 7L I /O 6L I /O 5L I /O 4L I/O 3L I/O 2L V SS I/O 1L I/O 0L VSS I /O 0R I / O1 R I / O2 R I/O 3R I/O 4R I/O 5R I/O 6R V DD I/O 7R I/O 8R I/O 9R I/O 10R
6.42 2
IDT70V9359/49L High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Pin Configurations(cont'd)(1,2,3,4)
70V9359/49BF BF100(5) 100-Pin fpBGA Top View(6)
A2 A3 A4
CNTRSTR
07/03 /02
A1
A5
A6
A7
A8
A9
A10
A8R
B1
A11R
B2
UBR
B3
Vss
B5
Vss
B6 B7
Vss
I/O13R I/O10R I/O17R
B8 B9 B10
B4
A6R
C1
A7R
C2
A10R A12R( 1) R/WR OER PL/FTR I/O12R I/O9R I/O6R
C3 C4 C5 C6 C7 C8 C9 C10
A3R
D1
A4R
D2
A5R
D3
A9R
D4
CE1R I/O16R I/O15R I/O11R I/O7R I/O3R
D5 D6 D7 D8 D9 D10
A0R
E1
CLKR
E2
A1R
E3 CNTENR F3
A2R
E4
LBR
E5
CE0R I/O14R I/O8R I/O5R I/O1R
E6 E7 E8 E9 E10
Vss
F1
A D SR
F2
A1L
F4
A D SL
F5
Vss
F6
I/O4R I/O2R I/O0R
F7 F8 F9
VDD
F10
Vss
G1 CNTENL H1
CLKL
G2
A0L
G3
A3L
G4
VDD
G5
Vss
G6
VDD
G7
I/O2L
G8
I/O1L
G9
I/O0L
G10
A4L
H2
A7L
H3
UBL
H4 H5
Vss
I/O13L
H6
NC
H7
I/O4L
H8
Vss
H9
I/O3L
H10
,
A2L
J1
A6L
J2
A11L
J3
CE0L
J4
CNTRST L
I/O15L I/O9L I/O7L
J6 J7 J8
I/O6L
J9
I/O5L
J10
J5
A5L
K1
A9L
K2
A12L(1) R/WL
K3 K4
OEL PL/FTL I/O12L I/O10L
K5 K6 K7 K8
Vss
K9
I/O8L
K10
A8L
A10L
LBL
CE1L
VDD
VDD
I/O16L I/O14L I/O11L I/O17L
5638 d rw 03
NOTES: 1. A12 is a NC for IDT70V9349. 2. All VDD pins must be connected to power supply. 3. All VSS pins must be connected to ground supply. 4. Package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch. 5. This package code is used to reference the package diagram. 6. This text does not indicate orientation of the actual part-marking.
6.42 3
IDT70V9359/49L High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Pin Names
Left Port C E0L, CE1L R/WL OEL A0L - A12L
(1)
Right Port C E0R, CE1R R/WR OER A0R - A12R
(1)
Names Chip Enables (3) Read/Write Enable Output Enable Add ress Data Input/Output Clo ck Upp er Byte Select(2) Lo wer Byte Select(2) Add ress Strobe Enable Counter Enable Counter Reset Flo w-Through / Pipeline Powe r (3.3V) Ground (0V)
5638 tbl 01
I/O0L - I/O17L CLKL U BL LBL AD SL CN TENL C NTRSTL FT/PIPEL
I/O0R - I/O17R CLKR U BR LBR AD SR CN TENR C NTRSTR FT/PIPER VDD VSS
NOTE: 1. A12 is a NC for IDT70V9349. 2 . LB and UB are single buffered regardless of state of FT/PIPE. 3 . CEo and CE1 are single buffered when FT/PIPE = VIL, CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
Tr uth Table IRead/Write and Enable Control(1,2,3)
OE X X X X X X L L L H CLK X CE0(5) H X L L L L L L L L CE1(5) X L H H H H H H H H UB(4) X X H L H L L H L X LB(4) X X H H L L H L L X R/ W X X X L L L H H H X Upper Byte I/O9-1 7 Hig h-Z Hig h-Z Hig h-Z DATAIN Hig h-Z DATAIN DATAOUT Hig h-Z DATAOUT Hig h-Z Lower Byte I/O0 -8 Hig h-Z Hig h-Z Hig h-Z Hig h-Z DATAIN DATAIN Hig h-Z DATAOUT DATAOUT Hig h-Z De sele cted Power Down De sele cted Power Down Bo th Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Re ad Upper Byte Only Re ad Lower Byte Only Re ad Both Bytes Outputs Disabled
5638 tbl 02
MODE
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal. 4 LB and UB are single buffered regardless of state of FT/PIPE. 5 . CEo and CE1 are single buffered when FT/PIPE = VIL. CEo and CE1 are double buffered when FT/PIPE = VIH, i.e. the signals take two cycles to deselect.
6.42 4
IDT70V9359/49L High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Tr uth Table IIAddress Counter Control(1,2)
E xtern al Add ress An X X X P revio us In ternal Add ress X An An + 1 X In ternal Add ress Used An An + 1 An + 1 A0 C LK ADS L(4 ) H H X CNTEN X L
(5 )
CNTRST H H H L
(4 )
I/O (3 ) DI/O (n) D I/O(n + 1 ) D I/O(n + 1 ) D I/O(0 ) E x te rn al Ad d re s s Used
M O DE
C o u nte r Enab le d -- In te rna l Ad d re s s g e n e rati o n E x te rn al Ad d re s s Blo c k e d -- C o u nte r disab le d (An + 1 re us e d ) C o u nte r Re s e t to Ad d re s s 0
5638 tbl 03
H X
NOTES: 1 . "H" = VIH, "L" = VIL, "X" = Don't Care. 2 . CE 0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3 . Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle. 4 . ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB. 5 . The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB.
Recommended Operating Temperature and Supply Voltage
Grade Comm ercial Industrial Ambient Temperature(1) 0OC to +70OC -40OC to +85OC GND 0V 0V VDD 3.3V + 0.3V 3.3V + 0.3V
5638 tbl 04
Recommended DC Operating Conditions
Symbol VDD VSS VIH V IL Parameter Sup ply Voltage Gro und Input High Voltage Input Low Voltage Min. 3. 0 0 2. 0 -0.3
(1)
Typ. 3. 3 0
____
Max. 3. 6 0 VDD+ 0.3V 0. 8
(2)
Unit V V V V
56 38 tbl 05
NOTES: 1 . This is the parameter TA. This is the "instant on" case temperature.
____
NOTES: 1 . VIL > -1.5V for pulse width less than 10 ns. 2 . VTERM must not exceed VDD+0.3V.
Absolute Maximum Ratings(1)
Symbol VTE RM(2) Rating Terminal Voltage with Respect to GND Temp e rature Und e r Bias Sto rag e Temp e rature DC Output Current Commerci al & Industrial -0.5 to +4.6 Uni t V
Capacitance(1)
Symbol CIN COUT
(3)
(TA = +25°C, f = 1.0MHZ)
Parameter Inp ut Capacitance Outp ut Capacitance Conditions(2) VIN = 3dV V OUT = 3dV Max. 9 10 Unit pF pF
5638 tbl 07
TB IAS TS TG IO UT
-55 to +125 -65 to +150 50
o
C C
o
mA
5638 tbl 06
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to VDD + 0.3V.
NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O.
6.42 5
Others parts begin by 70
70-1 70-2 70-3
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