|
|
Part: 70V9369
Category:
Interface and Interconnect
-> Multi-Ports
Description: 16K X 18 Sync, 3.3V Dual-port RAM, Pipelined/flow-through
Company: Integrated Device Technology, Inc.
Datasheet: Download 70V9369 datasheet File size : 115 kB
Request For quote: Find where to buy 70V9369
Datasheet text preview:
HIGH-SPEED 3.3V 16K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
.eatures:
x x
PRELIMINARY IDT70V9369L
x
x
x x
True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial: 7.5/9/12ns (max.) Industrial: 9ns (max.) Low-power operation IDT70V9369L Active: 500mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic
x
x
x x
x
Full synchronous operation on both ports 4ns setup to clock and 0ns hold on all control, data, and address inputs Data input, address, and control registers Fast 7.5ns clock to data out in the Pipelined output mode Self-timed write allows fast cycle time 12ns cycle time, 83MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (±0.3V) power supply Industrial temperature range (40°C to +85°C) is available for selected speeds Available in a 100-pin Thin Quad Flatpack (TQFP)
.unctional Block Diagram
R/WL
UBL CE0L
R/WR
UBR CE0R
CE1L
LBL OEL
1 0 0/1
1 0 0/1
CE1R
LBR OER
FT/PIPEL
0/1
1b 0b
ba
1a 0a
0a 1a
a
b
0b 1b
0/1
FT/PIPER
I/O9L-I/O17L I/O0L-I/O8L
I/O Control
I/O9R-I/O17R I/O Control I/O0R-I/O8R
A13L A0L CLKL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg.
A13R A0R CLKR
ADSL CNTENL CNTRSTL
ADSR CNTENR CNTRSTR
5648 drw 01
JANUARY 2002
1
©2002 Integrated Device Technology, Inc. DSC-5648/1
IDT70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Description:
The IDT70V9369 is a high-speed 16K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V9369 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 500mW of power.
Pin Configuration(1,2,3)
Index
A9L A10L A11L A12L A13L NC NC LBL UBL CE0L CE1L CNTRSTL R/WL OEL VDD FT/PIPEL I/O17L I/O16L VSS I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 2 74 3 73 1 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68
A8L A7L A6L A5L A4L A3L A2L A1L A0L CNTENL CLKL ADSL VSS Vss ADSR CLKR CNTENR A0R A1R A2R A3R A4R A5R A6R A7R
70V9369PF PN100-1(4) 100-Pin TQFP Top View(5)
67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
01/09/02
A8R A9R A10R A11R A12R A13R NC NC LBR UBR CE0R CE1R CNTRSTR R/WR VSS OER FT/PIPER I/O17R VSS I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R . 5648 drw 02
NOTES: 1 . All VDD pins must be connected to power supply. 2 . All VSS pins must be connected to ground. 3 . Package body is approximately 14mm x 14mm x 1.4mm. 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part-marking.
I/O9L I/O8L VDD I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L VSS I/O1L I/O0L VSS I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R VDD I/O7R I/O8R I/O9R I/O10R
6.42 2
IDT70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Pin Names
Left Port C E0L, CE1L R/WL OEL A0L - A13L I/O0L - I/O17L CLKL U BL LBL AD SL CN TENL C NTRSTL FT/PIPEL Right Port C E0R, CE1R R/WR OER A0R - A13R I/O0R - I/O17R CLKR U BR LBR AD SR CN TENR C NTRSTR FT/PIPER VDD VSS Names Chip Enables ( 2) Read/Write Enable Output Enable Add res s Data Input/Output Clo ck Upp er Byte Select( 1) Lo wer Byte Select( 1) Add res s Strobe Enable Counter Enable Counter Reset Flo w-Through / Pipeline Powe r (3.3V) Ground (0V)
5648 tbl 01
NOTES: 1 . LB and UB are single buffered regardless of state of FT/PIPE. 2 . CE 0 and CE1 are single buffered when FT/PIPE = VIL, CE 0 and CE1 are double buffered when FT/PIPE = VIH, i.e., the signals take two cycles to deselect.
Tr uth Table IRead/Write and Enable Control(1,2,3)
OE X X X X X X L L L H CLK X CE0 H X L L L L L L L L CE1 X L H H H H H H H H UB X X H L H L L H L L LB X X H H L L H L L L R/W X X X L L L H H H X Upper Byte I/O9-1 7 High-Z High-Z Hi gh-Z DATAIN Hi gh-Z DATAIN DATAOUT Hi gh-Z DATAOUT High-Z Lower Byte I/O0 -8 High-Z High-Z Hi gh-Z Hi gh-Z DATAIN DATAIN Hi gh-Z DATAOUT DATAOUT High-Z De sele cted Po wer Down De sele cted Po wer Down Bo th Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Re ad Upper Byte Only Re ad Lower Byte Only Re ad Both Bytes Outputs Disabled
5648 tbl 02
MODE
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal.
6.42 3
IDT70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM
Preliminary Industrial and Commercial Temperature Ranges
Tr uth Table IIAddress Counter Control(1,2,6)
Address An X X X Previous Address X An An + 1 X Addr Used An An + 1 An + 1 A0 CLK(6) AD S L
(4)
CN TEN X L
(5)
C NTRST H H H L
(4)
I/O(3) DI/O (n) DI/O(n+1) DI/O(n+1) DI/O(0) External Address Used
MODE
H H X
Counter Enabled--Internal Address generation E xternal Address Blocked--Counter disabled (An + 1 reused) Counter Reset to Address 0
5648 tbl 03
H X
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS and CNTRST are independent of all other signals including CE0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB. 6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
Recommended Operating Temperature and Supply Voltage
Grade Comme rcial Industrial Ambient Temperature(1) 0OC to +70OC -40OC to +85OC GND 0V 0V VDD 3.3V + 0.3V 3.3V + 0.3V
5648 tbl 04
Recommended DC Operating Conditions
Symbol VDD Vs s VIH V IL Parameter Sup ply Voltage Gro und Input High Voltage Input Low Voltage Min. 3. 0 0 2. 0V -0.3
(1)
Typ. 3. 3 0
____
Max. 3. 6 0 VDD+ 0.3V 0. 8
(2)
Unit V V V V
56 48 tbl 05
NOTES: 1 . This is the parameter TA. This is the "instant on" case temperature.
____
NOTES: 1 . VIL > -1.5V for pulse width less than 10 ns. 2 . VTERM must not exceed VDD +0.3V.
Absolute Maximum Ratings(1)
Sym bol VTE RM(2) Rating Terminal Voltage with Respect to GND Temp e rature Und e r Bias Sto rage Temp e rature DC Output Current Commerci al & Industrial -0.5 to +4.6 Uni t V
Capacitance(1)
Symbol CIN COUT
(3 )
(TA = +25°C, f = 1.0MHZ)
Parameter Inp ut Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
5648 tbl 07
TB IAS TS TG IO UT
-55 to +125 -65 to +150 50
o
C C
o
mA
5648 tbl 06
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . VTERM must not exceed VDD +0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to VDD + 0.3V.
NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O.
6.42 4
IDT70V9369L High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM
Preliminary Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temper ature and Supply Voltage Range (VDD = 3.3V ± 0.3V)
70V9369L Sym bol |ILI| |ILO| VO L VOH Parameter Inp ut Leakage Current(1) Outp ut Leakage Current Outp ut Low Voltage Outp ut High Voltage VDD = 3.6V, VIN = 0V to VDD C EO = VIH or CE1 = VIL, VOUT = 0V to VDD IO L = +4mA IOH = -4mA Test Conditions Mi n .
___
Max. 5 5 0.4
___
Unit µA µA V V
5648 tbl 08
___
___
2.4
NOTE: 1 . At VDD < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating Temper ature Supply Voltage Range(3) (VDD = 3.3V ± 0.3V)
70V9369L7 Com 'l Only Sym bol IDD Param eter Dy nam ic Operating Curre nt (Both Po rts Active) Stand b y Current (Bo th Ports - TTL Le v e l Inputs) Stand b y Curre nt (One Po rt - TTL Le v e l Inputs) Full Standby Curre nt (Both Po rts - CMOS Le v e l Inputs) Full Standby Curre nt (One Po rt - CMOS Le v e l Inputs) Test Condition C EL and CER= VIL, Outp uts Disabled, f = fMAX(1) C EL = CER = VIH f = fMAX(1) C E"A " = VIL and C E"B " = VIH(5) Ac tiv e Port Outputs Di s ab le d , f=fMAX(1) Bo th Ports CEL and C ER > VDD - 0.2V, V IN > VDD - 0.2V or V IN < 0.2V, f = 0(2) Version COM' L IND COM' L IND COM' L IND COM' L IND L L L L L L L L L L Typ. (4) 200
____
70V9369L9 Com 'l & Ind Typ. (4) 180 180 50 50 110 110 M ax. 260 280 100 120 190 205 3.0 6.0 180 195
70V9369L12 Com 'l Only Typ. (4) 150
____
M ax. 310
____
M ax. 230
____
Uni t mA
IS B1
65
____
130
____
40
____
80
____
mA
IS B2
140
____
245
____
100
____
175
____
mA
IS B3
0.4
____
3
____
0.4 0.4
0.4
____
3
____
mA
IS B4
COM' L C E"A " VDD - 0.2V(5) IND V IN > VDD - 0.2V or V IN < 0.2V, Active Port, Ou tp uts Disabled , f = fMAX(1)
130
____
235
____
100 100
90
____
165
____
mA
NOTES: 1 . At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2 . f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3 . Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4 . VDD = 3.3V, TA = 25°C for Typ, and are not production tested. IDD DC(f=0) = 90mA (Typ). 5 . CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX VDD - 0.2V CEX > VDD - 0.2V means CE0X > VDD - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port.
5648 tbl 09
6.42 5
Others parts begin by 70
70-1 70-2 70-3
|
|
|
