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Part: 70V9379
Category:
Interface and Interconnect
-> Multi-Ports
Description: 32K X 18 Sync, 3.3V Dual-port RAM, Pipelined/flow-through
Company: Integrated Device Technology, Inc.
Datasheet: Download 70V9379 datasheet File size : 115 kB
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Datasheet text preview:
HIGH-SPEED 3.3V 32K x 18 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Features:
x x
IDT70V9379L
x
x
x x
True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial: 7.5/9/12ns (max.) Low-power operation IDT70V9379L Active: 500mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic
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x x
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Full synchronous operation on both ports 4ns setup to clock and 0ns hold on all control, data, and address inputs Data input, address, and control registers Fast 7.5ns clock to data out in the Pipelined output mode Self-timed write allows fast cycle time 12ns cycle time, 83MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (±0.3V) power supply Industrial temperature range (40°C to +85°C) is available for selected speeds Available in a 128-pin Thin Quad Flatpack (TQFP)
Functional Block Diagram
R/WL
UBL CE0L
R/WR
UBR CE0R
CE1L
LBL OEL
1 0 0/1
1 0 0/1
CE1R
LBR OER
FT/PIPEL
0/1
1b 0b
ba
1a 0a
0a 1a
a
b
0b 1b
0/1
FT/PIPER
I/O9L-I/O17L I/O0L-I/O8L
I/O Control
I/O9R-I/O17R I/O Control I/O0R-I/O8R
A14L A0L CLKL Counter/ Address Reg. MEMORY ARRAY Counter/ Address Reg.
A14R A0R CLKR
ADSL CNTENL CNTRSTL
ADSR CNTENR CNTRSTR
4857 drw 01
JANUARY 2001
1
©2000 Integrated Device Technology, Inc. DSC-4857/2
IDT70V9379L High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Description:
The IDT70V9379 is a high-speed 32K x 18 bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times. With an input data register, the IDT70V9379 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 500mW of power.
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
A 10R A 11R A 12R A 13R A 14R NC NC NC LBR UB R CE 0R CE 1R CN TRSTR V CC GND R/WR OE R FT/PIPER GND I/O17R I/O16R I/O15R I/O14R V CC V CC I/O13R
Pin Configuration(1,2,3)
NC NC NC NC A9R A8R A7R A6R A5R A4R A3R A2R A1R A0R NC CNTENR CLKR ADSR GND VCC ADSL CL KL CNTENL NC A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
70V9379PRF PK-128-1(4) 128-Pin TQFP Top View(5)
A10L A11L A12L A13L A14L NC NC NC LBL UBL CE0L CE1L CNTRSTL VCC GND R/WL OEL FT/PIPEL GND I/O17L I/O16L I/O15L I/O14L VCC GND I/O13L
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
I/O12R I/O11R GND NC I/O10R I/O9R I/O8R I/O7R VCC I/O6R I/O5R I/O4R GND I/O3R VCC I/O2R I/O1R I/O0R GND VCC I/O0L I/O1L GND I/O2L I/O3L GND I/O4L I/O5L I/O6L I/O7L VCC I/O8L I/O9L I/ O10L NC VCC I/ O11L I/ O12L
4857 drw 02
NOTES: 1 . All Vcc pins must be connected to power supply. 2 . All GND pins must be connected to ground. 3 . Package body is approximately 14mm x 20mm x 1.4mm. 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part-marking.
6.42 2
IDT70V9379L High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Pin Names
Left Port C E0L, CE1L R/WL OEL A0L - A14L I/O0L - I/O17L CLKL U BL LBL AD SL CN TENL C NTRSTL FT/PIPEL Right Port C E0R, CE1R R/WR OER A0R - A14R I/O0R - I/O17R CLKR U BR LBR AD SR CN TENR C NTRSTR FT/PIPER VCC GND Names Chip Enables Read/Write Enable Output Enable Add res s Data Input/Output Clo ck Upp er Byte Select Lo wer Byte Select Add res s Strobe Enable Counter Enable Counter Reset Flo w-Through / Pipeline Powe r Ground
4857 tbl 01
Tr uth Table IRead/Write and Enable Control(1,2,3)
OE X X X X X X L L L H CLK X CE0 H X L L L L L L L L CE1 X L H H H H H H H H UB X X H L H L L H L L LB X X H H L L H L L L R/W X X X L L L H H H X Upper Byte I/O9-1 7 High-Z High-Z Hi gh-Z DATAIN Hi gh-Z DATAIN DATAOUT Hi gh-Z DATAOUT High-Z Lower Byte I/O0 -8 High-Z High-Z Hi gh-Z Hi gh-Z DATAIN DATAIN Hi gh-Z DATAOUT DATAOUT High-Z De sele cted Po wer Down De sele cted Po wer Down Bo th Bytes Deselected Write to Upper Byte Only Write to Lower Byte Only Write to Both Bytes Re ad Upper Byte Only Re ad Lower Byte Only Re ad Both Bytes Outputs Disabled
4857 tbl 02
MODE
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. ADS, CNTEN, CNTRST = X. 3. OE is an asynchronous input signal.
6.42 3
IDT70V9379L High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
Tr uth Table IIAddress Counter Control(1,2,6)
Address X An An X Previous Address X X Ap Ap Addr Used 0 An Ap Ap + 1 CLK AD S X L(4) H H CN TEN X X H L
(5)
C NTRST L H H H
I/O(3) DI/ O(0) DI/ O(n) DI/ O(p)
MODE Counte r Reset to Address 0 External Address Loaded into Counter External Address Blocked--Counter disabled (Ap reused)
DI/ O(p+ 1) Counte r Enabled--Internal Address generation
4857 tbl 03
NOTES: 1. "H" = VIH, "L" = VIL, "X" = Don't Care. 2. CE0, LB, UB, and OE = VIL; CE1 and R/W = VIH. 3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle. 4. ADS is independent of all other signals including CE0, CE1, UB and LB. 5. The address counter advances if CNTEN = VIL on the rising edge of CLK, regardless of all other signals including CE0, CE1, UB and LB. 6. While an external address is being loaded (ADS = VIL), R/W = VIH is recommended to ensure data is not written arbitrarily.
Recommended Operating Temper ature and Supply Voltage(1)
Grade Comme rcial Industrial Ambient Temperature(2) 0OC to +70OC -40OC to +85OC GND 0V 0V Vcc 3.3V + 0.3V 3.3V + 0.3V
4857 tbl 04
Recommended DC Operating Conditions
Symbol VCC GND VIH V IL Parameter Sup ply Voltage Gro und Input High Voltage Input Low Voltage Min. 3. 0 0 2. 0V -0.3
(1)
Typ. 3. 3 0
____
Max. 3. 6 0 VCC+ 0.3V 0. 8
(2)
Unit V V V V
48 57 tbl 05
NOTES: 1 . Industrial temperature: for specific speeds, packages and powers contact your sales office. 2 . This is the parameter TA. This is the "instant on" case temperature.
____
NOTES: 1 . VIL > -1.5V for pulse width less than 10 ns. 2 . VTERM must not exceed VCC +0.3V.
Absolute Maximum Ratings(1)
Sym bol VTE RM(2) Rating Terminal Voltage with Respect to GND Temp e rature Und e r Bias Sto rage Temp e rature DC Output Current Commerci al & Industrial -0.5 to +4.6 Uni t V
Capacitance(1)
Symbol CIN COUT
(3 )
(TA = +25°C, f = 1.0MHZ)
Parameter Inp ut Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 9 10 Unit pF pF
4857 tbl 07
TB IAS TS TG IO UT
-55 to +125 -55 to +150 50
o
C C
o
mA
4857 tbl 06
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2 . VTERM must not exceed VCC +0.3V for more than 25% of the cycle time or 10ns maximum, and is limited to VCC + 0.3V.
NOTES: 1. These parameters are determined by device characterization, but are not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V. 3. COUT also references CI/O.
6.42 4
IDT70V9379L High-Speed 32K x 18 Dual-Port Synchronous Pipelined Static RAM
Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating Temper ature and Supply Voltage Range (VCC = 3.3V ± 0.3V)
70V9379L Sym bol |ILI| |ILO| VO L VOH Parameter Inp ut Leakage Current(1) Outp ut Leakage Current Outp ut Low Voltage Outp ut High Voltage VCC = 3.6V, VIN = 0V to VCC C E = VIH or CE1 = VIL, VOUT = 0V to VCC IO L = +4mA IOH = -4mA Test Conditions Mi n .
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Max. 5 5 0.4
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Unit µA µA V V
4857 tbl 08
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2.4
NOTE: 1 . At Vcc < 2.0V input leakages are undefined.
DC Electrical Characteristics Over the Operating Temper ature Supply Voltage Range(3,6) (VCC = 3.3V ± 0.3V)
70V9379L7 Com 'l Only Sym bol ICC Param eter Dy namic Operating Curre nt (Both Po rts Active) Stand b y Current (Bo th Ports - TTL Le v e l Inputs) Stand b y Curre nt (One Po rt - TTL Le v e l Inputs) Full Standby Curre nt (Both Po rts - CMOS Le v e l Inputs) Full Standby Curre nt (One Po rt - CMOS Le v e l Inputs) Test Condition CEL and CER= VIL, Outp uts Disabled, f = fMAX(1) CEL = CER = VIH f = fMAX
(1)
70V9379L9 Com 'l Only Typ. (4) 180
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70V9379L12 Com 'l Only Typ. (4) 150
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Version COM' L IND COM' L IND COM' L IND COM' L IND L L L L L L L L L L
Typ. (4) 200
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Max. 310
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Max. 260
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Max. 230
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Uni t mA
IS B1
65
____
130
____
50
____
100
____
40
____
80
____
mA
IS B2
CE"A " = VIL and CE"B " = VIH(5) Ac tiv e Port Outputs Dis ab le d , f=fMAX(1) Bo th Ports CEL and CER > VCC - 0.2V, V IN > VCC - 0.2V or V IN < 0.2V, f = 0(2)
140
____
245
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110
____
190
____
100
____
175
____
mA
IS B3
0.4
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3
____
0.4
____
3
____
0.4
____
3
____
mA
IS B4
COM' L CE"A " VCC - 0.2V(5) IND V IN > VCC - 0.2V or V IN < 0.2V, Active Port, (1) Ou tp uts Disabled , f = fMAX
130
____
235
____
100
____
180
____
90
____
165
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mA
NOTES: 1 . At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/tCYC, using "AC TEST CONDITIONS" at input levels of GND to 3V. 2 . f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby. 3 . Port "A" may be either left or right port. Port "B" is the opposite from port "A". 4 . Vcc = 3.3V, TA = 25°C for Typ, and are not production tested. ICC DC(f=0) = 90mA (Typ). 5 . CEX = VIL means CE0X = VIL and CE1X = VIH CEX = VIH means CE0X = VIH or CE1X = VIL CEX VCC - 0.2V CEX > VCC - 0.2V means CE0X > VCC - 0.2V or CE1X < 0.2V "X" represents "L" for left port or "R" for right port. 6 . Industrial temperature: for specific speeds, packages and powers contact your sales office.
4857 tbl 09
6.42 5
Others parts begin by 70
70-1 70-2 70-3
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