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Part: 70V9389
Category:
Interface and Interconnect
-> Multi-Ports
Description: 64K X 18 Synch, 3.3V Dual-port RAM, Pipelined/flow-through
Company: Integrated Device Technology, Inc.
Datasheet: Download 70V9389 datasheet File size : 115 kB
Request For quote: Find where to buy 70V9389
Datasheet text preview:
HIGH-SPEED 3.3V 64K x18/x16 SYNCHRONOUS PIPELINED DUAL-PORT STATIC RAM
Features:
IDT70V9389/289L
True Dual-Ported memory cells which allow simultaneous access of the same memory location High-speed clock to data access Commercial: 6/7.5/9/12ns (max.) Industrial: 9ns (max.) Low-power operation IDT70V9389/289L Active: 500mW (typ.) Standby: 1.5mW (typ.) Flow-Through or Pipelined output mode on either port via the FT/PIPE pins Counter enable and reset features Dual chip enables allow for depth expansion without additional logic
Full synchronous operation on both ports 3.5ns setup to clock and 0ns hold on all control, data, and address inputs Data input, address, and control registers Fast 6.5ns clock to data out in the Pipelined output mode Self-timed write allows fast cycle time 10ns cycle time, 100MHz operation in Pipelined output mode Separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility LVTTL- compatible, single 3.3V (±0.3V) power supply Industrial temperature range (40°C to +85°C) is available for selected speeds Available in a 128-pin Thin Quad Flatpack (TQFP) and 100-pin Thin Quad Flatpack (TQFP)
Functional Block Diagram
R/WL
U BL C E0 L
R/WR UB R
CE0R
CE1L
L BL OEL
1 0 0/1
1 0 0/1
CE1R
LBR O ER
FT/PIPEL
0/1
1b 0b
ba
1a 0a
0a 1a
a
0b 1b b
0/1
FT/PIPER
I/O9L-I/O17L(2) I/O Control I/O0L-I/O8L(1) I/O Control
I/O9R-I/O17R(1)
I/O0R-I/O8R(1)
A15L A0L CLKL Counter/ Addres s Reg. MEMOR Y ARRAY Counter/ Address Reg.
A15R A 0R C LKR
AD SL CNTENL CNTRSTL
A DSR CNTENR CNTRSTR
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NOTE: 1 . I/O0X - I/O7X for IDT70V9289. 2 . I/O8X - I/O15X for IDT70V9289.
APRIL 2003
1
©2003 Integrated Device Technology, Inc. DSC-4856/3
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
The IDT70V9389/289 is a high-speed 64K x 18 (64K x 16) bit synchronous Dual-Port RAM. The memory array utilizes Dual-Port memory cells to allow simultaneous access of any address from both ports. Registers on control, data, and address inputs provide minimal setup and hold times. The timing latitude provided by this approach allows systems to be designed with very short cycle times.
Description:
With an input data register, the IDT70V9389/289 has been optimized for applications having unidirectional or bidirectional data flow in bursts. An automatic power down feature, controlled by CE0 and CE1, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 500mW of power.
Pin Configuration(1,2,3)
03/28/03
1 28 1 27 1 26 1 25 1 24 1 23 1 22 1 21 1 20 1 19 1 18 1 17 1 16 1 15 1 14 1 13 1 12 1 11 1 10 1 09 1 08 1 07 1 06 1 05 1 04 1 03
A 10R A 11R A 12R A 13R A 14R A 15R NC NC LB R UBR C E 0R C E 1R C N T R S TR V DD V SS R /W R O ER F T /P I P E R V SS I /O 1 7 R I /O 1 6 R I /O 1 5 R I /O 1 4 R V DD V DD I /O 1 3 R
NC NC NC NC A9R A8 R A7 R A6 R A5 R A4 R A3 R A2 R A1 R A0 R NC CNT E NR CLKR A DS R
VS S V DD
ADSL C LKL CNTENL NC A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
70V9389PRF PK-128-1(4 ) 128-Pin TQFP Top View(5)
A 1 0L A 1 1L A 1 2L A 1 3L A 1 4L A 1 5L NC NC L BL U BL C E 0L C E 1L C N T R S TL VDD VSS R /W L O EL F T / P I P EL VSS I / O 1 7L I / O 1 6L I / O 1 5L I / O 1 4L VDD VSS I / O 1 3L
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
I /O12R I /O11R
V SS
NC I /O10R I /O9R I /O8R I /O7R
V DD
I /O6R I /O5R I /O4R
V SS
I /O3R
V DD
I /O2R I /O1R I /O0R
V SS V DD
I /O0L I /O1L
V SS
I /O2L I /O3L
V SS
I /O4L I /O5L I /O6L I /O7L
V DD
I /O8L I /O9L I /O10 L NC
VD D
I /O11 L I /O12 L
4856 drw 02
NOTES: 1 . All VDD pins must be connected to power supply. 2 . All VSS pins must be connected to ground. 3 . Package body is approximately 14mm x 20mm x 1.4mm. 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part-marking.
6.42 2
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Pin Configurations(1,2,3)(con't.)
INDEX
A9 L A1 0 L A1 1 L A1 2 L A1 3 L A1 4 L A15L LBL UB L CE 0 L CE 1 L CNTRSTL R/WL OEL V DD FT/PIPEL I/O17L I/O16L VSS I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 72 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
A 8L A 7L A 6L A 5L A 4L A 3L A 2L A 1L A 0L CNT ENL CL K L A DS L VSS VS S A DS R CLK R C N T EN R A 0R A1 R A2 R A3 R A 4R A 5R A 6R A 7R
03/2 8/03
70 V 93 89 P F P N 1 0 0 - 1 (4 ) 1 0 0 - P in T Q F P Top View (5)
51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A8R A9R A10R A11R A12R A13R A14R A15R LBR UBR CE0R CE1R CNTRSTR R/WR VSS OER FT/PIPER I/O17R VSS I/O16R I/O15R I/O14R I/O13R I/O12R I/O11R
4856 drw 02a
,
NOTES: 1 . All VDD pins must be connected to power supply. 2 . All VSS pins must be connected to ground. 3 . Package body is approximately 14mm x 14mm x 1.4mm 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part-marking.
I/O9 L I/O 8L V DD I/O 7L I/O 6L I/O 5L I/O 4L I/O 3L I/O 2L V SS I/O1L I/O 0L VSS I/O 0R I/O 1R I/O 2R I/O3R I/O4R I/O5R I/O6R VD D I/O 7R I/O 8R I/O 9R I/O1 0R
6.42 3
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Pin Configurations(1,2,3)(con't.)
A 10R A 11R A 12R A 13R A 14R A 15R NC NC LB R UBR C E 0R C E 1R C N T R S TR V DD V SS R /W R O ER F T /P I P E R V SS I /O 1 5 R I /O 1 4 R I /O 1 3 R I /O 1 2 R V DD V DD I /O 1 1 R 12 8 12 7 12 6 12 5 12 4 12 3 12 2 12 1 12 0 11 9 11 8 11 7 11 6 11 5 11 4 11 3 11 2 11 1 11 0 10 9 10 8 10 7 10 6 10 5 10 4 10 3
03/28/03
NC NC NC NC A9R A8R A7 R A6 R A5 R A4 R A3 R A2 R A1 R A0 R NC C NTENR CLKR A DS R
VSS VDD
ADSL C LKL C NTENL NC A0L A1L A2L A3L A4L A5L A6L A7L A8L A9L NC NC NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
70V9289PRF PK-128-1(4) 128-Pin TQFP Top View(5)
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
I/ O1 0R I/ O9 R
VS S
NC I/ O8 R NC NC I/ O7 R
VD D
I/ O6 R I/ O5 R I/ O4 R
VS S
I/ O3 R
VD D
I/ O2 R I/ O1 R I/ O0 R
VS S VD D
I/ O0 L I/ O1 L
VS S
I/ O2 L I/ O3 L
VS S
I/ O4 L I/ O5 L I/ O6 L I/ O7 L
VD D
NC NC I/O8L NC
V DD
I/O9L I/O10L
4856 drw 02b
NOTES: 1 . All VDD pins must be connected to power supply. 2 . All VSS pins must be connected to ground. 3 . Package body is approximately 14mm x 20mm x 1.4mm. 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part-marking.
A 10L A 11L A 12L A 13L A 14L A 15L NC NC LBL UBL C E 0L C E 1L C N T R S TL VD D V SS R /W L O EL F T/P IP E L V SS I /O 1 5 L I /O 1 4 L I /O 1 3 L I /O 1 2 L VD D V SS I /O 1 1 L
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
6.42 4
IDT70V9389/289L High-Speed 3.3V 64K x18/x16 Dual-Port Synchronous Pipelined Static RAM
Industrial & Commercial Temperature Ranges
Pin Configurations(1,2,3)(con't.)
Index
A9 L A10L A11L A12L A13L A14L A15L NC NC LBL UBL CE0L CE1L CNTRSTL VDD R/WL OE L FT/PIPEL V SS I/O15L I/O14L I/O13L I/O12L I/O11L I/O10L
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 1 75 2 74 3 73 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
A8 L A7 L A 6L A 5L A 4L A 3L A2 L A 1L A 0L C N TE N L C LK L ADSL VS S ADSR C LK R CN T E N R A 0R A 1R A 2R A3 R A 4R A 5R A 6R A 7R A 8R
03/28/03
IDT70V9289PF PN100-1(4) 100-Pin TQFP Top View(5)
51 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 4 5 46 47 48 49 50
A9R A10R A11R A12R A13R A14R A15R NC NC LBR UB R CE0R CE1R . CNTRSTR V SS R/WR OER FT/PIPER V SS I/O15R I/O14R I/O13R I/O12R I/O11R I/O10R
4856 dr w 02c
NOTES: 1 . All VDD pins must be connected to power supply. 2 . All VSS pins must be connected to ground. 3 . Package body is approximately 14mm x 14mm x 1.4mm 4 . This package code is used to reference the package diagram. 5 . This text does not indicate orientation of the actual part-marking.
I/O9 L I/O8 L VDD I/O 7L I/O 6L I/O5 L I/O4 L I/O 3L I/O 2L V SS I/O IL I/O 0L V SS I/O0 R I/O1 R I/O2 R I/O3 R I/O4 R I/O 5R I/O6 R VDD I/O7 R I/O8 R I/O9 R NC
6.42 5
Others parts begin by 70
70-1 70-2 70-3
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