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Part: 71016
Category:
Memory
-> SRAM
-> Async. SRAM
Description: 64K X 16 Static RAM
Company: Integrated Device Technology, Inc.
Datasheet: Download 71016 datasheet File size : 115 kB
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Datasheet text preview:
CMOS Static RAM 1 Meg (64K x 16-Bit)
Features
64K x 16 advanced high-speed CMOS Static RAM Equal access and cycle times Commercial and Industrial: 12/15/20ns One Chip Select plus one Output Enable pin Bidirectional data inputs and outputs directly TTLcompatible Low power consumption via chip deselect Upper and Lower Byte Enable Pins Commercial and industrial product available in 44-pin Plastic SOJ package and 44-pin TSOP package
IDT71016
x x
Description
The IDT71016 is a 1,048,576-bit high-speed Static RAM organized as 64K x 16. It is fabricated using IDT's high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71016 has an output enable pin which operates as fast as 7ns, with address access times as fast as 12ns. All bidirectional inputs and outputs of the IDT71016 are TTL-compatible and operation is from a single 5V supply. Fully static asynchronous circuitry is used, requiring no clocks or refresh for operation. The IDT71016 is packaged in a JEDEC standard 44-pin Plastic SOJ and 44-pin TSOP Type II.
x x
x x x
Functional Block Diagram
OE Output Enable Buffer
A0 - A15
Address Buffers
Row / Column Decoders
I/O 15 Chip Enable Buffer 8 High Byte I/O Buffer 8
,
CS
I/O 8
WE
Write Enable Buffer
64K x 16 Memory Array
16
Sense Amps and Write Drivers 8 Low Byte I/O Buffer 8
I/O 7
I/O 0
BHE Byte Enable Buffers BLE 3210 drw 01
FEBRUARY 2001
1
©2000 Integrated Device Technology, Inc. DSC-3210/7
IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Pin Configurations
A4 A3 A2 A1 A0 CS I/O 0 I/O 1 I/O 2 I/O 3 VCC VSS I/O 4 I/O 5 I/O 6 I/O 7 WE A15 A14 A13 A12 NC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 SO44-1 SO44-2 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 A5 A6 A7 OE BHE BLE I/ O 15 I/ O 14 I/ O 13 I/ O 12 VSS VCC I/ O 11 I/ O 10 I/ O 9 I/ O 8 NC A8 A9 A10 A11 NC
32 1 0 drw 0 2
Pin Descriptions
A0 - A15 CS WE OE BHE BLE I/O0 - I/O15 V CC VS S Ad d re s s Inputs Chip Select Write Enable Outp ut Enable Hig h Byte Enable Lo w Byte Enable Data Input/Output 5.0V Power Gro und Inp ut Inp ut Inp ut Inp ut Inp ut Inp ut I/O Pwr Gnd
3210 tbl 01
,
SOJ/TSOP Top View
Tr uth Table (1)
CS H L L L L L L L L OE X L L L X X X H X WE X H H H L L L H X BLE X L H L L L H X H BHE X H L L L H L X H I/O0 - I/O7 Hig h-Z DATAOUT Hig h-Z DATAOUT DATAIN DATAIN Hig h-Z Hig h-Z Hig h-Z I/O8 - I/O15 Hig h-Z Hig h-Z DATAOUT DATAOUT` DATAIN Hig h-Z DATAIN Hig h-Z Hig h-Z Function De s ele c te d - Standby Low Byte Read Hig h Byte Read Wo rd Read Wo rd Write Low Byte Write Hig h Byte Write Outp uts Disabled Outp uts Disabled
3210 tbl 02
NOTE: 1 . H = VIH, L = VIL, X = Don't care.
6.42 2
IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM (2 ) TA TB IA S TS TG PT IOUT Rating Term inal Voltage with Respect to GND Operating Temperature Tem perature Under Bias Storage Tem perature Pow er Dissipation DC Output Current Value -0.5 to +7.0 0 to +70 -55 to +125 -55 to +125 1.25 50 Unit V
o o
Recommended Operating Temperature and Supply Voltage
Grade Com m ercial Temperature 0° C to +70°C 40° C to +85°C GN D 0V 0V V CC 5.0V ± 10% 5.0V ± 10%
3 210 tbl 04
C C C
Industrial
o
Recommended DC Operating Conditions
Symbol V CC Parameter Supply Voltage Ground Input High Voltage Input Low Voltage Min. 4.5 0 2.2 -0. 5(1 ) Typ. 5.0 0
___ _ ___ _
W mA
M ax. 5.5 0 VDD +0.5 0.8
Unit V V V V
G ND
NOTES: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed VCC + 0.5V.
3210 tbl 03
VI H VI L
3210 tbl 05 NOTE: 1 . VIL (min.) = 1.5V for pulse width less than tRC/2, once per cycle.
Capacitance
Symbol CI N CI/O
(TA = +25° C, f = 1.0MHz, SOJ Package)
Parameter(1) Input Capacitance I/O Capacitance Conditions VIN = 3dV VOUT = 3dV Max. 6 7 Unit pF pF
(VCC = 5.0V ± 10%, Commercial and Industrial Temperature Range)
Symbol |ILI| |ILO| VO L VO H Parameter Input Leakage Current Output Leakage Current Output Low Voltage Output High Voltage Test Conditions VCC = Max., VIN = GND to VCC VCC = Max., CS = VIH, VOUT = GND to VCC IOL = 8mA, VCC = Min. IOH = -4mA, VCC = Min. Min.
__ _ __ _ __ _
DC Electrical Characteristics
3210 tbl 06 NOTE: 1 . This parameter is guaranteed by device characterization, but not production tested.
Max. 5 5 0.4
__ _
Unit µA µA V V
3210 tbl 07
2.4
DC Electrical Characteristics(1)
(VCC = 5.0V ± 10%, VLC = 0.2V, VHC = VCC0.2V)
71016S12 Symbol I CC IS B Parameter D y nam ic Operating Current CS VIH, Outputs Open, VCC = Max., F = fMAX(2 ) Standby Power Supply Current (CMOS Level) CS > VHC, Outputs Open, VCC = Max., f = 0(2 ) VIN VHC Com'l. 210 60 10 Ind. 210 60 10 71016S15 Com'l. 180 50 10 Ind. 180 50 10 71016S20 Com'l. 170 45 10 Ind. 170 45 10 Unit mA mA mA
ISB1
NOTES: 1 . All values are maximum guaranteed values. 2 . fMAX = 1/tRC (all address inputs are cycling at fMAX); f = 0 means no address input lines are changing .
3210 tbl 08
6.42 3
IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
AC Test Conditions
Input Pulse Levels Input Rise/Fall Times Input Timing Reference Levels Output Reference Levels AC Test Load GND to 3.0V 1.5ns 1.5V 1.5V See Figure 1, 2 and 3
3210 tbl 09
AC Test Loads
5V 480
5V 480 DATA OUT 255
3210 drw 03
DATA OUT 30pF*
5pF*
255
3210 drw 04
,
,
*Including jig and scope capacitance. Figure 1. AC Test Load Figure 2. AC Test Load (for tCLZ, tOLZ, tCHZ, tOHZ, tOW, and tWHZ)
7 tAA, tACS (Typical, ns) 5 4 3 2 1
· · · · · ·
·
6
,
CAPACITANCE (pF)
3210 drw 05
8 20 40 60 80 100 120 140 160 180 200
Figure 3. Output Capacitive Derating
6.42 4
IDT71016, CMOS Static RAM 1 Meg (64K x 16-bit)
Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
Symbol READ CYCLE tRC t AA t A CS tCLZ
(1 )
(VCC = 5.0V ± 10%, Commercial and Industrial Range)
71016S12 71016S15 Min. Max. 71016S20 Min. Max. Unit Min. Max.
Parameter
Read Cycle Time Address Access Time Chip Select Access Time Chip Select Low to Output in Low-Z Chip Select High to Output in High-Z Output Enable Low to Output Valid Output Enable Low to Output in Low-Z Output Enable High to Output in High-Z Output Hold from Address Change Byte Enable Low to Output Valid Byte Enable Low to Output in Low-Z Byte Enable High to Output in High-Z
12
___ _
___ _
15
___ _
___ _
20
___ _
___ _
ns ns ns ns ns ns ns ns ns ns ns ns
12 12
___ _
15 15
___ _
20 20
___ _
___ _
___ _
___ _
4
___ _
5
___ _
5
___ _
tCHZ(1 ) t OE tOLZ(1 ) tOHZ(1 ) t OH t BE tBLZ(1 ) tBHZ(1 ) WRITE CYCLE tWC tAW tCW t BW t AS tWR tWP tDW tDH t OW
(1 )
6 7
___ _
6 8
___ _
8 10
___ _
___ _
___ _
___ _
0
___ _
0
___ _
0
___ _
6
___ _
6
___ _
8
___ _
4
___ _
4
___ _
5
___ _
7
___ _
8
___ _
10
___ _
0
___ _
0
___ _
0
___ _
6
6
8
Write Cycle Time Ad dress Valid to End of Write Chip Select Low to End of Write Byte Enable Low to End of Write Address Set-up Time Address Hold from End of Write Write Pulse Width Data Valid to End of Write Data Hold Time Write Enable High to Output in Low-Z Write Enable Low to Output in High-Z
12 9 9 9 0 0 9 7 0 1
___ _
___ _
15 10 10 10 0 0 10 8 0 1
___ _
___ _
20 12 12 12 0 0 12 10 0 1
___ _
___ _
ns ns ns ns ns ns ns ns ns ns ns
3210 tbl 10
___ _ ___ _ ___ _
___ _ ___ _ ___ _
___ _ ___ _ ___ _
___ _ ___ _ ___ _
___ _ ___ _ ___ _
___ _ ___ _ ___ _
___ _ ___ _
___ _ ___ _
___ _ ___ _
___ _
___ _
___ _
tWHZ(1 )
6
6
8
NOTE: 1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
Timing Waveform of Read Cycle No. 1(1,2,3)
tRC ADDRESS tAA tOH DATAOUT PREVIOUS DATAOUT VALID tOH DATAOUT VALID
3210 drw 06
NOTES: 1 . WE is HIGH for Read Cycle. 2 . Device is continuously selected, CS is LOW. 3 . OE, BHE, and BLE are LOW.
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6.42 5
Others parts begin by 71
71-1
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