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Part: 71215
Category:
Description:
Company: Integrated Device Technology, Inc.
Datasheet: Download 71215 datasheet File size : 115 kB
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BiCMOS Static RAM 240K (16K x 15-Bit) Cache-Tag RAM for the PentiumTM Processor
Featur es
x
IDT71215
x x x x x x x x x x x
16K x 15 Configuration 12 TAG Bits 3 Separate I/O Status Bits (Valid, Dirty, Write Through) Match output uses Valid bit to qualify MATCH output High-Speed Address-to-Match comparison times 8/9/10/12ns over commercial temperature range B R D Y circuitry included inside the Cache-Tag for highest speed operation Asynchronous Read/Match operation with Synchronous Write and Reset operation Separate W E for the TAG bits and the Status bits WE Separate O E for the TAG bits, the Status bits, and B R D Y OE BRDY Synchronous R E S E T pin for invalidation of all Tag RESET entries Dual Chip selects for easy depth expansion with no performance degredation I/O pins both 5V TTL and 3.3V LVTTL compatible with VCCQ pins PWRDN pin to place device in low-power mode PWRDN Packaged in a 80-pin Thin Plastic Quad Flat Pack (TQFP).
De s c r i p t i o n
The IDT71215 is a 245,760-bit Cache Tag Static RAM, organized 16K x 15 and designed to support the Pentium and other Intel processors at bus speeds up to 66MHz. There are twelve common I/O TAG bits, with the remaining three bits used as status bits. A 12bit comparator is on-chip to allow fast comparison of the twelve
stored TAG bits and the current Tag input data. An active HIGH MATCH output is generated when these two groups of data are the same for a given address. This high-speed MATCH signal, with tADM as fast as 8ns, provides the fastest possible enabling of secondary cache accesses. The three separate I/O status bits (VLD, DTY, and WT) can be configured for either dedicated or generic functionality, depending on the SFUNC input pin. With SFUNC LOW, the status bits are defined and used internally by the device, allowing easier determination of the validity and use of the given Tag data. SFUNC HIGH releases the defined internal status bit usage and control, allowing the user to configure the status bit information to fit his system needs. A synchronous RESET pin, when held LOW at a rising clock edge, will reset all status bits in the array for easy invalidation of all Tag addresses. The IDT71215 also provides the option for Burst Ready (BRDY) generation within the cache tag itself, based upon MATCH, VLD bit, WT bit, and external inputs provided by the user. This can significantly simplify cache controller logic and minimize cache decision time. Match and Read operations are both asynchronous in order to provide the fastest access times possible, while Write operations are synchronous for ease of system timing. The IDT71215 uses a 5V power supply on VCC with separate VCCQ pins provided for the outputs to offer compliance with both 5V TTL and 3.3V LVTTL Logic levels. The PWRDN pin offers a low-power standby mode to reduce power consumption by 90%, providing significant system power savings. The IDT71215 is fabricated using IDT's high-performance, highreliability BiCMOS technology and is offered in a space-saving 80-pin Thin Plastic Quad Flat Pack (TQFP) package.
Pin Descriptions
A0 A13 CS1, CS2 WET WES OET OES RESET PWRDN SFUNC W/R VLDIN/S1IN DTYIN/S2IN WTIN/S3IN Address Inputs Chip Selects Write Enable Tag Bits Write Enable Status Bits Output Enable Tag Bits O utput Enable Status Bits Status Bit Reset Pow erdow n Mode Control Pin Stat us Bit Function Control Pin Input Input Input Input Input Input Input Input Input CLK BRDYH BRDYOE BRDYIN BRDY TAG 0 TAG11 VLDOUT /S1OUT DTYOUT /S2OUT WTOUT /S3OUT M ATCH V CC V CCQ VS S Sy stem Clock BRDY Force High BRDY Output Enable Additional BRDY Input Burst Ready Tag Data Input/Outputs Valid Bit/S1 Bit Output Dirty Bit/S2 Bit Output Write Through Bit/S3 Bit Output M atch +5V Power Output Buffer Power Ground Input Input Input Input Output I/O Output Output Output Output Pw r QPw r Gnd
3075 tbl 01
Pentium is a trademark of Intel Corporation.
Write/ Read Input from Processor Input Valid Bit/S1 Bit Input Dirty Bit/S2 Bit Input Write Through Bit/S3 Bit Input Input Input Input
OCTOBER 1999
1
DSC-3075/04
©1999 Integrated Device Technology, Inc.
IDT71215 BiCMOS Static RAM 240K (16K x 15-Bit) Cache-Tag RAM for the PentiumTM Processor
Commercial Temperature Range
Pin Configuration
VLDIN / S1IN BRDYOE PWRDN
RESET
TAG11
TAG10
WES
OES
OET
VSS
CLK
CS2
CS1
VSS VSS VSS VSS DTYIN / S2IN WTIN / S3IN A0 A1 A2 VCC VSS A3 A4 A5 A6 A7 VSS VSS VSS VSS
1
80
VSS
TAG9
VSS VSS VSS TAG8 TAG7 TAG6 VLDOUT / S1OUT VCCQ VSS BRDY MATCH VSS VCCQ WTOUT / S3OUT TAG5 TAG4 NC VSS VSS VSS
PN80-1
A10
A11
W/R
VCC
BRDYH
VSS
A12
A13
VSS
BRDYIN
VSS
TAG1
VCCQ
VCCQ TAG2
VCC
WET
VCC
VSS
SFUNC
DTYOUT / S2OUT
TAG0
TAG3
A8
A9
3075 drw 01
TQFP Top View
6.42 2
IDT71215 BiCMOS Static RAM 240K (16K x 15-Bit) Cache-Tag RAM for the PentiumTM Processor
Commercial Temperature Range
Functional Block Diagram
ADDR (0:13) Reg 0 1 16K x 12 MEMORY TAG BITS 16K x 3 MEMORY STATUS BITS
CS1 CS2 Reg DataIN Register SA SA DataIN Register VLD/S1IN DTY/S2IN WT/S3IN
TAG (0:11) OET
VLD/S1OUT DTY/S2OUT WRITE (pos) PULSE GENERATOR WT/S3OUT
WET Reg WES CLK RESET (neg) PULSE GENERATOR COMPARE OES
RESET PWRDN SFUNC MATCH W/R BRDYH BRDYIN BRDY Reg
BRDYOE
3075 drw 02
6.42 3
IDT71215 BiCMOS Static RAM 240K (16K x 15-Bit) Cache-Tag RAM for the PentiumTM Processor
Commercial Temperature Range
Tr uth Table Chip Select, Reset, and Power-Down Functions (1,2)
CS1 CS2 RESET PWRDN CLK WET WES BRDYOE TAG VLDOUT DTYOUT WTOUT MATCH BRDY OPERATION POWER CHIP SELECT FUNCTION H X L X L H X X X H H H X X X X X X X X X X X X Hi-Z Hi-Z -- Hi-Z Hi-Z -- Hi-Z Hi-Z -- Hi-Z Hi-Z -- Hi-Z Hi-Z -- Hi-Z Hi-Z -- Deselected Deselected Selected Activ e Activ e Activ e
RESET FUNCTION L L H X X X H H X L X X L L L L L L H H H H H H H H H H L X H H H H X L L H X X X X Hi-Z Hi-Z Hi-Z Hi-Z -- -- L(3 ) L
(3 )
L(3 ) L
(3 )
L(3 ) L
(3 )
L(3 ) L
(3 )
H Hi-Z Hi-Z Hi-Z -- --
Reset Status Reset Status Reset Status Reset Status Not Allowed Not Allowed
Activ e Activ e Activ e Activ e -- --
Hi-Z Hi-Z -- --
Hi-Z Hi-Z -- --
Hi-Z Hi-Z -- --
Hi-Z Hi-Z -- --
POWE R-DOWN FUNCTION X X X L X H H X Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Pow er-dow n Standby
3075 tbl 02
NOTES: 1. "H" = VIH, "L" = VIL, "X" = don't care, "" = unrelated. 2. OET, OES, W/R, BRDYH, BRDYIN and SFUNC are "X" for this table. 3. OES is LOW.
Tr uth Table Read and Write Functions(1,2)
OET OES WET WES CLK W/ R TAG VLDIN DTYIN WTIN VLDOUT DTYOUT WTOUT MATCH OPERATION READ FUNCTION L X H X X L X H H X X X X X X X X X X X X X X X DOUT -- Hi-Z -- -- -- -- -- -- -- -- -- -- -- -- -- -- DOUT -- Hi-Z -- DOUT -- Hi-Z -- DOUT -- Hi-Z DOUT DOUT DOUT DOUT Read TAG I/O Read Status Bits TAG I/O Disable Status Disabled
WRITE FUNCTION H L X X X X L H L L X X X X L L X X X X DI N -- -- -- -- -- DI N DI N -- -- DI N DI N -- -- DI N DI N DOUT -- DOUT (3) Hi-Z DOUT -- DOUT (3) Hi-Z DOUT -- DOUT (3) Hi-Z L -- L L Write TAG I/O Not Allowed Write Status Bits Write Status Bits
3075 tbl 03
NOTES: 1. "H" = VIH, "L" = VIL, "X" = don't care, "" = unrelated. 2. This table applies when CS1 is LOW and CS2, RESET, and PWRDN are HIGH. BRDYOE, BRDYH, BRDYIN and SFUNC are "X" for this table. 3. DOUT in this case is the same as DIN; that is, the input data is written through to the outputs during the write operation.
6.42 4
IDT71215 BiCMOS Static RAM 240K (16K x 15-Bit) Cache-Tag RAM for the PentiumTM Processor
Commercial Temperature Range
Tr uth Table Match Function(1,2,3)
CS1 H X L L L L L L L CS2 X L H H H H H H H SFUNC X X X X X X L L H OET X X X L H X H H H WET X X X H L X H H H WES X X X X X L H H H TAG Hi-Z Hi-Z -- DOUT DIN -- TAGIN TAGIN TAGIN VLD(4 ) -- -- -- -- -- DIN L H X DTY(4 ) -- -- -- -- -- DI N -- -- -- WT(4 ) -- -- -- -- -- DIN -- -- -- MATCH Hi-Z Hi-Z DOUT L L L L M M OPERATION Deselected Deselected Selected Read Tag I/O Write Tag I/O Write Status Bits Inv alid Data -- Dedicated Status Bits M atch -- Dedicated Status Bits M atch -- Generic Status Bits
3075 tbl 04
NOTES: 1. "H" = VIH, "L" = VIL, "X" = don't care, "" = unrelated. 2. M = HIGH if TAGIN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address. 3. PWRDN and RESET are HIGH for this table. W/R, BRDYH, BRDYOE, BRDYIN, OES, and CLK are "X". 4. This column represents the stored memory cell data for the given Status bit at the selected address.
Truth Table BRDY Function(1,2,3,5)
BRDYOE B RDYIN(6 ) H L L L L L L L L L L L X L H H H H H H H H H H OET X X L X X X X X H H H H WET X X X L X X X X H H H H WES BRDYH W/R X X X X L X X X H H H H X X X X X H X X L L L L X X X X X X X H X L X X SFUNC X X X X X X L L L L L H VLD(4 ) DTY(4 ) WT(4 ) X X X X DI N X L X H H H X -- -- -- -- DI N -- -- -- -- -- -- -- X X X X DI N X X H L X X X TAG -- -- DOUT DI N -- -- -- -- TAGIN TAGIN TAGIN TAGIN MATCH BRDY -- X L L L X L X M M M M Hi-Z L H H H H H H M M M M OPERATION BRDY Disabled Ext BRDY Input(7 ) Read TAG Write TAG Write Status Force BRDY HIGH Inv alid TAG Write Through Com pare Com pare Com pare Com pare
3075 tbl 05
NOTES: 1. "H" = VIH, "L" = VIL, "X" = don't care, "" = unrelated. 2. M = HIGH if TAGIN equals the memory contents at that address; M = LOW if TAGIN does not equal the memory contents at that address. 3. PWRDN and RESET are HIGH for this table. CLK and OES are "X". 4. This column represents the stored memory cell data for the given Status bit at the selected address. 5. CS1 is LOW, CS2 is HIGH for this table. 6. BRDYIN is a synchronous input; thus the inputs noted in the table must be applied during a rising CLK edge. 7. BRDYIN will be a factor in determining the BRDY output in all cases except when BRDYH is HIGH and there is a valid MATCH. In that case, BRDY will be LOW(Valid).
6.42 5
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