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Part: 7143
Category:
Interface and Interconnect
-> Multi-Ports
Description: 2K X 16 Dual-port RAM
Company: Integrated Device Technology, Inc.
Datasheet: Download 7143 datasheet File size : 2479 kB
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Datasheet text preview:
HIGH SPEED 2K X 16 DUAL-PORT SRAM
Features
x x x x x x
IDT7133SA/LA IDT7143SA/LA
x
x
x
x
High-speed access Military: 25/35/45/55/70/90ns (max.) Industrial: 25/35/55ns (max.) Commercial: 20/25/35/45/55/70/90ns (max.) Low-power operation IDT7133/43SA Active: 1150mW (typ.) Standby: 5mW (typ.) IDT7133/43LA Active: 1050mW (typ.) Standby: 1mW (typ.) Versatile control for write: separate write control for lower and upper byte of each port MASTER IDT7133 easily expands data bus width to 32 bits or more using SLAVE IDT7143 On-chip port arbitration logic (IDT7133 only)
x x
BUSY output flag on IDT7133; BUSY input on IDT7143 Fully asynchronous operation from either port Battery backup operation2V data retention TTL-compatible; single 5V (±10%) power supply Available in 68-pin ceramic PGA, Flatpack, PLCC and 100pin TQFP Military product compliant to MIL-PRF-38535 QML Industrial temperature range (40°C to +85°C) is available for selected speeds
Description
The IDT7133/7143 are high-speed 2K x 16 Dual-Port Static RAMs. The IDT7133 is designed to be used as a stand-alone 16-bit Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the IDT7143 "SLAVE" Dual-Port in 32-bit-or-more word width systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-bit-or-wider
Functional Block Diagram
R/WLUB CEL R/WRUB CER
R/WLLB OE L
R/WRLB OER
I/O8L - I/O15L I/O0L - I/O7L BUSYL (1) A10L A0L ADDRESS DECODER
11
I/O CONTROL
I/O CONTROL
I/O8R - I/O15R I/O0R - I/O 7R BUSYR
(1)
MEMORY ARRAY
ADDRESS DECODER
11
A10R A0R
CE L
ARBITRATION LOGIC (IDT7133 ONLY)
CER
2746 drw 01
NOTE: 1. IDT7133 (MASTER): BUSY is open drain output and requires pull-up resistor. IDT7143 (SLAVE): BUSY is input.
JUNE 2000
1
©2000 Integrated Device Technology, Inc. DSC 2746/11
IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
memory system applications results in full-speed, error-free operation without the need for additional discrete logic. Both devices provide two independent ports with separate control, address, and I/O pins that permit independent, asynchronous access for reads or writes to any location in memory. An automatic power down feature, controlled by CE, permits the on-chip circuitry of each port to enter a very low standby power mode. Fabricated using IDT's CMOS high-performance technology, these devices typically operate on only 1,150mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each port typically consuming 200µW for a 2V battery. The IDT7133/7143 devices have identical pinouts. Each is packed in a 68-pin ceramic PGA, 68-pin flatpack, 68-pin PLCC and 100-pin TQFP. Military grade product is manufactured in compliance with the latest revision of MIL-PRF-38535 QML, making it ideally suited to military temperature applications demanding the highest level of performance and reliability.
Pin Configurations(1,2,3)
INDEX
I/O9L I/O10L I/O11L I/O12L I/O13L I/O14L I/O15L VC C(1) GND(2) I/O0R I/O1R I/O2R I/O3R I/O4R I/O5R I/O6R I/O7R
I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L I/O1L I/O0L VCC(1) R/WLUB R/WLLB OEL A10L A9L A8L A7L
9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 IDT7133/ 43 J68-1 / F68-1(4) 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45
68-Pin PLCC/Flatpack Top View(5)
44 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
A6L A5L A4L A3L A2L A1L A0L BUSYL CEL CER BUSYR A0R A1R A2R A3R A4R A5R
2746 drw 02
I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R I/O15R GND(2) R/WRUB R/WRLB OER A10R A9R A8R A7R A6R
Index
6.42 2
I/O7R I/O8R I/O9R I/O10R I/O11R I/O12R I/O13R I/O14R GND I/O1 5R OER R/WRLB GND N/C CER R/WRUB N/C N/C N/C A10R A9R A8R A7R A6R A5R
NOTES: 1. Both VCC pins must be connected to the power supply to ensure reliable operation. 2. Both GND pins must be connected to the ground supply to ensure reliable operation. 3. J68-Package body is approximately 0.95 in x 0.95 in x 0.17 in. F68-Package body is approximately 1.18 in x 1.18 in x 0.16 in. PN100-Package body is approximately 14mm x 14mm x 1.4mm. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
N/C N/C N/C N/C I/O1 0L I/O1 1L I/O1 2L I/O1 3L GND I/O1 4L I/O1 5L VCC GND I/O0R I/O1R I/O2R VCC I/O3R I/O4R I/O5R I/O6R N/C N/C N/C N/C
1 2 3 4 5 6 7 8 9
10 0 99 98 97 96 95 94 93 92 91 90 89 8 8 87 8 6 85 8 4 83 8 2 81 8 0 79 78 77 76 75 74 73 72 71 70 69 68 67
I/O9L I/O8L I/O7L I/O6L I/O5L I/O4L I/O3L I/O2L GND I/O1L I/O0L OEL VCC R/WL LB N/C CEL R/WLUB N/C N/C N/C A10 L A9L A8L A7L A6L
10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
IDT7133/43PF PN100-1(4) 100-Pin TQFP Top View(5 )
66 65 64 63 62 61 60 59 58 57 56 55 54 53 52
25 51 26 27 28 29 30 31 32 33 34 35 36 37 3 8 39 4 0 41 4 2 43 4 4 45 4 6 47 48 49 50
N/C N/C N/C N/C A5L A4L A3L A2L A1L A0L N/C BUSYL GND N/C BUSYR N/C A0R A1R A2R A3R A4R N/C N/C N/C N/C
274 6 drw 03
,
IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Pin Configurations(1,2,3) (con't.)
51 50 48 46 44 42 40 38 36
11
53
A6L
52
A5L
49
A3L
47
A1L
45
BUSYL
43
CER
41
A0R
39
A2R
37
A4R
35 34
10
55
A8L
54
A7L
A4L
A2L
A0L
CEL
BUSYR
A1R
A3R
A5R
32
A6R
33
09
A10L
57 56
A9L
A8R
30
A7R
31
08
R/WLLB
59
OEL
58
A10R
28
A9R
29
07
VCC(1) R/WLUB
61 60
R/WRLB
OER
27
IDT7133/43G GU68-1(4) 68-Pin PGA Top View(5)
26
06
I/O1L
63
I/O0L
62
GND(2) R/WRUB
24 25
05
I/O3L
65
I/O2L
64
I/O14R
22
I/O15R
23
04
I/O5L
67
I/O4L
66
I/O12R
20
I/O13R
21
03
I/O7L
68 1
I/O6L
3 5 7 9 11 13 15
I/O10R
18
I/O11R
19
02
I/O8L
2
I/O9L
4
I/O11L
6
I/O13L
8
I/O15L
GND(2)
10
I/O1R
12
I/O3R
14
I/O5R
16
I/O8R
17
I/O9R
01 Pin 1 Designator A
I/O10L B
I/O12L C
I/O14L D
VCC(1) E
I/O0R F
I/O2R G
I/O4R H
I/O6R J
I/O7R K L
2746 drw 04
NOTES: 1. Both VCC pins must be connected to the power supply to ensure reliable operation. 2. Both GND pins must be connected to the ground supply to ensure reliable operation. 3. Package body is approximately 1.18 in x 1.18 in x 0.16 in. 4. This package code is used to reference the package diagram. 5. This text does not indicate orientation of the actual part-marking.
Pin Names
Left Port C EL R/WLUB R/WLLB OEL A0 L - A10L I/O0 L - I/O15L BUSYL Right Port C ER R/WRUB R/WRLB OER A0R - A10R I/O0R - I/O15R BUSYR VCC GND Chip Enable Uppe r Byte Read/Write Enable Lo we r Byte Read/Write Enable Output Enable Addres s Data Input/Output Busy Flag Powe r Gro und
2746 tbl 01
Names
3 6.42
IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings(1)
Symbol VTERM(2) Rati ng Terminal Voltage with Respect to GND Tempe rature Und e r Bias Sto rag e Tempe rature Po we r Dis s ip ation DC Output Current Commercial & Industrial -0. 5 to +7.0 Mi litary -0. 5 to +7.0 Unit V
Maximum Operating Temperatur e and Supply Voltage(1,2)
Grade Military Ambient Temperature -55OC to +125OC 0 C to +70 C -40 C to +85 C
O O O O
GND 0V 0V 0V
Vcc 5.0V + 10% 5.0V + 10% 5.0V + 10%
2746 tbl 04
TB IA S TS TG PT(3) IO UT
-55 to +125 -65 to +150 2.0 50
-65 to +135 -65 to +150 2.0 50
o
C C
Commercial Indus trial
o
W mA
2746 tbl 02
NOTES: 1 . This is the parameter TA. This is the "instant on" case temperature.
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. VTERM must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to Vcc + 10%.
Recommended DC Operating Conditions
Sym bol VCC GND VIH V IL Parameter Sup p ly Voltage Gro und Inp ut High Voltage Inp ut Low Voltage Mi n. 4.5 0 2.2 -0. 5
(1)
Typ. 5.0 0
____ ____
Max. 5.5 0 6.0
(2)
Uni t V V V V
2746 tbl 05
0.8
Capacitance (TA = +25°C, f = 1.0mhz)
Symbol CIN COUT Parameter(1) Input Capacitance Output Capacitance Conditions(2) VIN = 3dV VOUT = 3dV Max. 11 11 Unit pF pF
2746 tbl 03
NOTES: 1. VIL (min.) = -1.5V for pulse width less than 10ns. 2. VTERM must not exceed Vcc + 10%.
NOTES: 1. This parameter is determined by device characterization but is not production tested. 2. 3dV references the interpolated capacitance when the input and output switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating Temper ature and Supply Voltage Range (Either port, VCC = 5.0V ± 10%)
7133SA 7143SA Symbol |ILI| |ILO| V OL V OL VOH Parameter Input Leakage Current
(1)
7133LA 7143LA Min .
___
Test Conditions VCC = 5.5V, VIN = 0V to VCC C E = VIH, VOUT = 0V to VCC IOL = 4mA IOL = 16mA IOH = -4mA
Min .
___
Max. 10 10 0.4 0.5
___
Max. 5 5 0.4 0.5
___
Unit µA µA V V V
2746 tbl 06
Outp ut Leakage Current Outp ut Low Voltage (I/O0-I/O15) Open Drain Output Low Voltage (BUSY) Outp ut High Voltage
___
___
___
___
___
___
2.4
2.4
NOTE: 1. At Vcc < 2.0V, input leakages are undefined.
6.42 4
IDT7133SA/LA, IDT7143SA/LA High-Speed 2K x 16 Dual-Port RAM
Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Operating Temperature and Supply Voltage Range(2) (VCC = 5.0V ± 10%)
7133X 20 7143X 20 Com'l Only Symbol ICC Parameter Dy namic Operating Curre nt (Bo th Ports Active) Test Condition C E = VIL, Outputs Disabled f = fMAX
(3)
7133X 25 7143X 25 Com'l, Ind & Military Typ. (1) 250 230 250 230 25 25 25 25 140 100 140 100 1.0 0.2 1.0 0.2 140 120 140 120 Max. 300 270 330 300 80 70 90 80 200 170 230 190 15 4 30 10 190 170 220 200
7133X 35 7143X 35 Com'l, Ind & Military Typ. (1) 240 210 240 220 25 25 25 25 120 100 120 100 1.0 0.2 1.0 0.2 120 100 120 100 Max. 295 250 325 295 70 60 75 65 180 160 200 180 15 4 30 10 170 150 190 170
2 746 tbl 07a
Versi on COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND S L S L S L S L S L S L S L S L S L S L
Typ. (1) 250 230
____ ____
Max. 310 280
____ ____
Unit mA
IS B1
Standb y Current (Bo th Ports - TTL Lev el Inputs)
C EL and CER = VIH f = fMAX(3)
25 25
____ ____
80 70
____ ____
mA
IS B2
Standb y Current (One Port - TTL Lev el Inputs)
C E"A " = VIL and CE"B" = VIH(4) f= fMAX(3) Ac tive Port Outputs Disabled
140 120
____ ____
200 180
____ ____
mA
IS B3
Full Standby Current (Bo th Ports CMOS Level Inputs)
Bo th Ports CEL and C ER > VCC - 0.2V VIN > VCC - 0.2V or VIN VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V Ac tive Port Outputs Disabled f = fMAX(3)
1.0 0.2
____ ____
15 5
____ ____
mA
IS B4
Full Standby Current (One Port CMOS Level Inputs)
140 120
____ ____
190 170
____ ____
mA
7133X45 7143X45 Com'l & Military Symbol ICC Parameter Dy namic Operating Curre nt (Bo th Ports Active) Test Condition C E = VIL, Outputs Disabled f = fMAX(3) Versi on COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND COM'L MIL & IND S L S L S L S L S L S L S L S L S L S L Typ. (1) 230 210 230 210 25 25 25 25 120 100 120 100 1. 0 0. 2 1. 0 0. 2 120 100 120 100 Max. 290 250 320 290 75 65 80 70 190 170 210 190 15 4 30 10 180 160 200 180
7133X55 7143X55 Com'l, Ind & Military Typ. (1) 230 210 230 210 25 25 25 25 120 100 120 100 1. 0 0. 2 1. 0 0. 2 120 100 120 100 Max. 285 250 315 285 70 60 80 70 180 160 210 190 15 4 30 10 170 150 200 180
7133X 70/90 7143X 70/90 Com'l & Military Typ. (1) 230 210 230 210 25 25 25 25 120 100 120 100 1. 0 0. 2 1. 0 0. 2 120 100 120 100 Max. 280 250 310 280 70 60 75 65 180 160 200 180 15 4 30 10 170 150 190 170
2746 tbl 07b
Unit mA
IS B1
Standb y Current (Bo th Ports - TTL Lev el Inputs)
C EL and CER = VIH f = fMAX
(3)
mA
IS B2
Standb y Current (One Port - TTL Lev el Inputs)
C E"A " = VIL and CE"B" = VIH(4) f= fMAX(3) Ac tive Port Outputs Disabled
mA
IS B3
Full Standby Current (Bo th Ports CMOS Level Inputs)
Bo th Ports CEL and C ER > VCC - 0.2V VIN > VCC - 0.2V or VIN VCC - 0.2V(5) VIN > VCC - 0.2V or VIN < 0.2V Ac tive Port Outputs Disabled f = fMAX(3)
mA
IS B4
Full Standby Current (One Port CMOS Level Inputs)
mA
NOTES: 1. VCC = 5V, TA = +25°C for Typ., and are not production tested. ICCDC = 180mA (typ.) 2. 'X' in part number indicates power rating (SA or LA) 3. At f = fMAX, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/ tRC, and using "AC Test Conditions" of input levels of GND to 3V. 4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby. 5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
5 6.42
Others parts begin by 71
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