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Part: 7210
Category:
Logic
Description: 16x16 Parallel Multiplier-accumulator
Company: Integrated Device Technology, Inc.
Datasheet: Download 7210 datasheet File size : 3700 kB
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Datasheet text preview:
IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER ACCUMULATOR
COMMERCIAL TEMPERATURE RANGE
16-BIT PARALLEL CMOS MULTIPLIER-ACCUMULATOR
IDT7210L
FEATURES:
· 16 x 16 parallel multiplier-accumulator with selectable accumulation and subtraction · High-speed: 20ns multiply-accumulate time · IDT7210 features selectable accumulation, subtraction, rounding and preloading with 35-bit result · IDT7210 is pin and function compatible with the TRW TDC1010J, TMC2210, Cypress CY7C510, and AMD AM29510 · Performs subtraction and double precision addition and multiplication · Produced using advanced CMOS high-performance technology · TTL-compatible · Available in PLCC · Speeds available: L20/25/35
DESCRIPTION:
The IDT7210 is a high-speed, low-power 16 x 16-bit parallel multiplieraccumulator that is ideally suited for real-time digital signal processing applications. Fabricated using CMOS silicon gate technology, this device offers a very low-power alternative to existing bipolar and NMOS counterparts, with only 1/7 to 1/10 the power dissipation and exceptional speed (25ns maximum) performance. A pin and functional replacement for TRW's TDC1010J, the IDT7210 operates from a single 5 volt supply and is compatible with standard TTL logic levels. The architecture of the IDT7210 is fairly straightforward,
featuring individual input and output registers with clocked D-type flip-flop, a preload capability which enables input data to be preloaded into the output registers, individual three-state output ports for the Extended Product (XTP) and Most Significant Product (MSP) and a Least Significant Product output (LSP) which is multiplexed with the Y input. The XIN and YIN data input registers may be specified through the use of the Two's Complement input (TC) as either a two's complement or an unsigned magnitude, yielding a full-precision 32-bit result that may be accumulated to a full 35-bit result. The three output registers Extended Product (XTP), Most Most Significant Product (MSP) and Least Significant Product (LSP) are controlled by the respective TSX, TSM and TSL input lines. The LSP output can be routed through YIN ports. Accumulate input (ACC) enables the device to perform either a multiply or a multiply-accumulate function. In the multiply-accumulate mode, output data can be added to or subtracted from previous results. When the Subtraction (SUB) input is active simultaneously with an active ACC, a subtraction can be performed. The double precision accumulated result is rounded down to either a single precision or single precision plus 3-bit extended result. In the multiply mode, the Extended Product output (XTP) is sign extended in the two's complement mode or set to zero in the unsigned mode. The Round (RND) control rounds up the Most Significant Product (MSP) and the 3-bit Extended Product (XTP) outputs. When Preload input (PREL) is active, all the output buffers are forced into a high-impedance state (see Preload truth table) and external data can be loaded into the output register by using the TSX, TSL and TSM signals as input controls.
FUNCTIONAL BLOCK DIAGRAM
C LKX X IN (X 1 5 - X0)
16
A C C , SUB, R N D , TC
4
Y IN C L K Y ( Y 1 5 - Y0/P15 - P0)
16
X R E G IS T E R
CONTRO L R E G IS T E R
Y R E G IS T E R
M U L T I P L I E R ARRAY
32 +
TSL PREL
+/ A C C U M U LA T O R
16 35 35
C LK P
X T M P REGISTER
3
M S P REGISTER
L S P REGISTER
TSX PREL
3 16
TSM
XTPOUT (P 3 4 - P32)
M SP OUT ( P 3 1 - P16)
COMMERCIAL TEMPERATURE RANGE
c 2001 Integrated Device Technology, Inc.
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
DECEMBER 2001
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DSC-2018/1
IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER ACCUMULATOR
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION
P 1 0 ,Y 1 0
P 1 1 ,Y 1 1
P 1 2 ,Y 1 2
P 1 3 ,Y 1 3
P 1 4 ,Y 1 4
P 1 5 ,Y 1 5
45
P 2 , Y2
P 3 ,Y 3
P 4 ,Y 4
P 5 ,Y 5
P 6 ,Y 6
P 7 ,Y 7
P 8 ,Y 8
P 9 ,Y 9
GND
GND
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
44
P 1 , Y1 6 1 P 0 , Y0 6 2 X0 63 X1 64 X2 65 X3 66 X4 67 X5 68 X6 1 X7 2 X8 3 X9 4 X10 5 X11 6 X12 7 X13 8 X14 9 J68-1
P16
43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27
P17 P18 P19 P20 P21 P22 P23 P24 P25 P26 P27 P28 P29 P30 P31 P32 P33
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
X15
TSX
PREL
C LKX
C LKY
PLCC TOP VIEW
2
C LKP
AC C
SUB
RND
TSM
TSL
V cc
V cc
V cc
V cc
P34
TC
IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER ACCUMULATOR
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Pin Name X0 - 15 Y0 - 15/ P0 - 15 P16 - 31 P32 - 34 CLKX CLKY CLKP TSX TSM TSL PREL ACC I/O I I/O I/O I/O I I I I I I I I Description Data Inputs Multiplexed I/O port. Y0 - 15 are data inputs and can be used to preload LSP register on PREL = 1. P0 - 15 are LSP register outputs - enabled by TSL. MSP register outputs - enabled by TSM. MSP register can be preloaded when PREL = 1. XTP register outputs - enabled by TSX. XTP register can be preloaded through these inputs when PREL = 1. Input data X0 - 15 loaded in X input register on CLKX rising edge Input data Y0 - 15 loaded in Y input register on CLKY rising edge Output data loaded into output register on rising edge of CLKP. TSX = 0 enables XTP outputs, TSX = 1 tristates P32 - 34 lines TSM = 0 enables MSP outputs, TSM = 1 tristates P16 - 31 lines TSL = 0 enables LSP outputs, TSL = 1 tristates P0 - 15 lines When PREL= 1 data is input on P0 - 15 lines. When PREL = 0, inputs on these lines are ignored. This input is loaded into the control register on the rising edge of (CLKX + CLKY). When ACC = 1 and SUB = 0 an accumulate operation is performed. When ACC = 1 and SUB = 1, a subtract operation is performed. When ACC = 0, the SUB input is a don't care and the device acts as a simple multipler with no accumulation. SUB I This input is loaded into the control register on the rising edge of (CLKX + CLKY). This input is active only when ACC = 1. When SUB = 1 the contents of the output register are subtracted from the result and stored back in the output register. When SUB = 0 the contents of the output register are added to the result and stored back in the output register. TC RND I I This input is loaded into the control register on the rising edge of (CLKX + CLKY). When TC = 1, the X and Y input are assumed to be in two's complement form. When TC = 0, X and Y inputs are assumed to be in unsigned magnitude form. This input is loaded into the control register on the rising edge of (CLKX + CLKY). RND is inactive when low. RND = 1, adds a "1" to the most significant bit of the LSP, to round MSP and XTP data.
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IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER ACCUMULATOR
COMMERCIAL TEMPERATURE RANGE
PRELOAD TRUTH TABLE
PREL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 TSX 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 TSM 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 TSL 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 XTP Q Q Q Q Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z Hi-Z PL PL PL PL MSP Q Q Hi-Z Hi-Z Q Q Hi-Z Hi-Z Hi-Z Hi-Z PL PL Hi-Z Hi-Z PL PL LSP Q Hi-Z Q Hi-Z Q Hi-Z Q Hi-Z Hi-Z PL Hi-Z PL Hi-Z PL Hi-Z PL
NOTES ON TWO'S COMPLEMENT FORMATS
1. In two's complement notation, the location of the binary point that signifies the separation of the fractional and integer fileds is just after the sign, between the sign bit (-20) and the next significant bit for the multiplier inputs. This same format is carried over to the output format, except that the extended significance of the integer filed is provided to extend the utility of the accumulator. In the case of the output rotation, the output binary point is located between the20 and 21 bit positions. The location of the binary point is arbitrary, as long as there is consistency with both the input and output formats. The number filed can be considered entirely integer with the binary point just to the right of the least significant bit for the input, product and the accumulated sum. 2. When in the non-accumulating mode, the first four bits (P34 to P31) will all indicate the sign of the product. Additionally, the P30 term will also indicate the sign with one exception, when multiplying -1 x -1. With the additional bits that are available in this multiplier, the 1 x 1 is a valid operation that yields a +1 product. 3. In operations that require the accumulation of single products or sum of products, there is no change in format. To allow for a valid summation beyond that available for a single multiplication product, three additional significant bits (guard bits) are provided. This is the same as if the product was accumulated off-chip in a separate 35-bit wide adder. Taking the sign at the most significant bit position will guarantee that the largest number field will be used. When the accumulated sum only occupies the right hand portion of the accumulator, the sign will be extended into the lesser significant bit positions.
NOTES: Hi Z = Output buffers at high-impedance (output disabled) Q = Output buffers at low impedance. Contents of output register will be transferred to output pins. P L = Output buffers at high-impedance or output disabled. Preload data supplied externally at output pins will be loaded into the output register at the rising edge of CLKP.
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VCC VTERM TA TBIAS TSTG IOUT Description Power Supply Voltage Terminal Voltage with Respect to GND Operating Temperature Temperature Under Bias Storage Temperature DC Output Current Max 0.5 to +7 0.5 to VCC + 0.5 0 to +70 55 to +125 55 to +125 50 Unit V V °C °C °C mA
CAPACITANCE (TA = +25°C, F = 1.0MHz)
Symbol CI N COUT Parameter(1) Input Capacitance Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 10 12 Unit pF pF
NOTE: 1 . This parameter is sampled and not 100% tested.
NOTE: 1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
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IDT7210L 16 x 16 PARALLEL CMOS MULTIPLIER ACCUMULATOR
COMMERCIAL TEMPERATURE RANGE
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, VCC = 5V ± 10%
Symbol VIH VIL ILI ILO VOH VOL(4) IOS ICC(2) ICCQ1 ICCQ2 ICC/f(2,3) Parameter Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Output HIGH Voltage Output LOW Voltage Output Short Circuit Current Operating Power Supply Current Quiescent Power Supply Current Quiescent Power Supply Current Increase in Power Supply Current Test Conditions(1) Guaranteed Logic HIGH Level Guaranteed Logic LOW Level VCC = Max., VIN = 0 to VCC VCC = Max., Outputs Disabled , VOUT = 0 to VCC VCC = Min., IOH = 2mA VCC = Min., IOL = 4mA VCC = Max., VO = GND VCC = Max., Outputs Enabled, f = 10MHz(2), CL = 50pF VIN VIH, VIN VIL VIN VCC - 0.2V, VIN 0.2V VCC = Max., Outputs Disabled Min. 2 -- -- -- 2.4 -- -20 -- -- -- -- Typ.(1) -- -- -- -- -- -- -- 45 20 4 -- Max. -- 0.8 10 10 -- 0.4 -100 90 30 10 6 Unit V V µA µA V V mA mA mA mA mA/MHz
NOTES: 1 . Typical implies VCC = 5V and TA = +25°C. 2 . ICC is measured at 10MHz and VIN = 0 to 3V. For frequencies greater than 10MHz, the following equation is used for the commercial range: ICC = 90+ 6(f 10)mA, where f = operating frequency in MHz. 3 . For frequencies greater than 10MHz, guaranteed by design, not production tested. 4 . IOL = 4mA for tMA > 55ns. 5 . For conditions shown as Max. or Min., use appropriate value specified under electrical characteristics.
AC ELECTRICAL CHARACTERISTICS
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0°C to +70°C, VCC = 5V ± 10%
Symbol tMA tD tENA tDIS tS tH tPW tHCL Parameter Multiply-Accumulate Time(2) Output Delay(2) 3-State Enable Time 3-State Disable Time(1) Input Register Set-up Time Input Register Hold Time Clock Pulse Width Relative Hold Time 7210L20 Min. 2 2 -- -- 10 3 9 0 Max. 20 18 18 18 -- -- -- -- Min. 2 2 12 3 10 0 7210L25 Max. 25 20 20 20 2 2 12 3 10 0 7210L35 Min. Max. 35 25 25 25
Unit ns ns ns ns ns ns ns ns
NOTES: 1 . Transition is measured ±500mV from steady state voltage. 2 . Minimum delays guaranteed but not tested
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