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Part: 72V3612
Category:
Memory
-> FIFO
Description: 64 X 36 X 2 Syncbififo, 3.3V
Company: Integrated Device Technology, Inc.
Datasheet: Download 72V3612 datasheet File size : 843 kB
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Datasheet text preview:
3.3 VOLT CMOS SyncBiFIFOTM 64 x 36 x 2
FEATURES:
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IDT72V3612
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Two independent clocked FIFOs (64 x 36 storage capacity each) buffering data in opposite directions Supports clock frequencies up to 83 MHz Fast access times of 8ns Free-running CLKA and CLKB can be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Mailbox bypass Register for each FIFO Programmable Almost-Full and Almost-Empty Flags Microprocessor interface control logic EFA , FFA , AEA , and AFA flags synchronized by CLKA EFB , FFB , AEB , and AFB flags synchronized by CLKB
Passive parity checking on each port Parity generation can be selected for each port Available in 132-pin plastic quad flat package (PQF), or space saving 120-pin thin quad flat package (TQFP) Pin and functionally compatible version of the 5V operating IDT723612 Industrial temperature range (40°C +85°C) is available ° °
DESCRIPTION:
The IDT72V3612 is a pin and functionally compatible version of the IDT723612, designed to run off a 3.3V supply for exceptionally low-power consumption. This device is a monolithic high-speed, low-power CMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 83 MHz
FUNCTIONAL BLOCK DIAGRAM
CLKA CSA W/RA ENA MBA Port-A Control Logic Mail 1 Register Parity Gen/Check MBF1 PEFB PGB
Parity Generation
Input Register
RST ODD/ EVEN Device Control
RAM ARRAY 64 x 36
Output Register
36
Write Pointer FFA AFA
36
Read Pointer EFB AEB
Status Flag Logic FIFO1 Programmable Flag Offset Register FIFO2 Status Flag Logic Read Pointer Write Pointer
36
FS0 FS1 A0 - A35 EFA AEA
B0 - B36 FFB AFB
Parity Generation
Output Register
RAM ARRAY 64 x 36
PGA Parity Gen/Check
Mail 2 Register CLKB CSB W/RB ENB MBB
4659 drw 01
PEFA MBF2
Input Register
Port-B Control Logic
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2003
DSC-4659/1
IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
and has read access times as fast as 8ns. The FIFO operates in IDT Standard mode. Two independent 64 x 36 dual-port SRAM FIFOs on board the chip buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (Almost-Full and Almost-Empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices can be used in parallel to create wider data paths. This device is a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. The Full Flag (FFA, FFB) and Almost-Full (AFA, AFB) flag of a FIFO are two-stage synchronized to the port clock that writes data to its array. The Empty Flag (EFA, EFB) and Almost-Empty (AEA, AEB) flag of a FIFO are two stage synchronized to the port clock that reads data from its array. The IDT72V3612 is characterized for operation from 0°C to 70°C. Industrial temperature range (40°C to +85°C) is available by special order. This device is fabricated using IDT's high speed, submicron CMOS technology.
PIN CONFIGURATIONS
AFA FFA CSA ENA CLKA W/RA VCC PGA PEFA GND MBF2 MBA FS1 FS0 ODD/EVEN RST GND NC NC NC NC MBB MBF1 GND PEFB PGB VCC W/RB CLKB ENB CSB FFB AFB
*
VCC A24 A25 A26 GND A27 A28 A29 VCC A30 A31 A32 GND A33 A34 A35 GND B35 B34 B33 GND B32 B31 B30 VCC B29 B28 B27 GND B26 B25 B24 VCC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
GND AEA EFA A0 A1 A2 GND A3 A4 A5 A6 VCC A7 A8 A9 GND A10 A11 VCC A12 A13 A14 GND A15 A16 A17 A18 A19 A20 GND A21 A22 A23
18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
*
116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
GND AEB EFB B0 B1 B2 GND B3 B4 B5 B6 VCC B7 B8 B9 GND B10 B11 VCC B12 B13 B14 GND B15 B16 B17 B18 B19 B20 GND B21 B22 B23
Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
4659 drw 02
NOTES: 1. NC - No internal connection 2. Uses Yamaichi socket IC51-1324-828
PQFP(2) (PQ132-1, order code: PQF) TOP VIEW
2
IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATIONS (CONTINUED)
A24 A25 A26 VCC A27 A28 A29 GND A30 A31 A32 A33 A34 A35 GND B35 B34 B33 B32 B31 B30 GND B29 B28 B27 VCC B26 B25 B24 B23
A23 A22 A21 GND A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 GND A9 A8 A7 VCC A6 A5 A4 A3 GND A2 A1 A0 EFA AEA
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
B22 B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 GND B9 B8 B7 VCC B6 B5 B4 B3 GND B2 B1 B0 EFB AEB AFB
AFA FFA CSA ENA CLKA W/RA VCC PGA PEFA MBF2 MBA FS1 FS0 ODD/EVEN RST GND NC NC NC NC MBB MBF1 PEFB PGB VCC W/RB CLKB ENB CSB FFB
TQFP (PN120-1, order code: PF) TOP VIEW 3
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
4659 drw 03
NOTE: 1 . NC - No internal connection
IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol A0-A35 AEA AEB AFA AFB B0-B35 CLKA Name Port A Data Port A Almost-Empty Flag Port B Almost-Empty Flag Port A Almost-Full Flag Port B Almost-Full Flag Port B Data. Port A Clock I/O I/O O (Port A) O (PortB) 36-bit bidirectional data port for side A. Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in the FIFO2 is less than or equal to the value in the offset register, X. Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is less than or equal to the value in the offset register, X. Description
O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty (Port A) locations in FIFO1 is less than or equal to the value in the offset register, X. O Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty (Port B) locations in FIFO2 is less than or equal to the value in the offset register, X. I/O I 36-bit bidirectional data port for side B. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. EFA, FFA, AFA, and AEA are synchronized to the LOW-toHIGH transition of CLKA. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. EFB, FFB, AFB, and AEB are synchronized to the LOW-toHIGH transition of CLKB. CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH.
CLKB
Port B Clock
I
CSA CSB EFA
Port A Chip Select Port B Chip Select Port A Empty Flag
I I
O EFA is synchronized to the LOW-to-HIGH transition of CLKA. When EFA is LOW, FIFO2 is empty, (Port A) and reads from its memory are disabled. Data can be read from FIFO2 to the output register when EFA is HIGH. EFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after data is loaded into empty FIFO2 memory. O EFB is synchronized to the LOW-to-HIGH transition of CLKB. When EFB is LOW, the FIFO1 is (Port B) empty, and reads from its memory are disabled. Data can be read from FIFO1 to the output register when EFB is HIGH. EFB is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO1 memory. I I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
EFB
Port B Empty Flag
ENA ENB FFA
Port A Enable Port B Enable Port A Full Flag
O FFA is synchronized to the LOW-to-HIGH transition of CLKA. When FFA is LOW, FIFO1 is full, (Port A) and writes to its memory are disabled. FFA is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after reset. O FFB is synchronized to the LOW-to-HIGH transition of CLKB. When FFB is LOW, FIFO2 is full, (Port B) and writes to its memory are disabled. FFB is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after reset. I I The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which selects one of four preset values for the Almost-Full flag and Almost-Empty flag. A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output, and a LOW level selects FIFO2 output register data for output. A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output, and a LOW level selects FIFO1 output register data for output. MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-toHIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH when the device is reset.
FFB
Port B Full Flag
FS1, FS0 MBA
Flag Offset Selects Port A Mailbox Select Port B Mailbox Select Mail1 Register Flag
MBB
I
MBF1
O
4
IDT72V3612 3.3V, CMOS SyncBiFIFOTM 64 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Symbol MBF2 Name Mail2 Register Flag I/O O Description MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-toHIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset. Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled for a read operation. When any byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is setup by having W/RA LOW, MBA HIGH, and PGA HIGH, the PEFA flag is forced HIGH regardless of the A0-A35 inputs. When any byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as B0-B8, B9-B17, B18-B26, B27-B35 with the most significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is setup by having W/RB LOW, MBB HIGH, and PGB HIGH, the PEFB flag is forced HIGH regardless of the state of the B0-B35 inputs. Parity is generated for data reads from port A when PGA is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as A0-A8, A9-A17, A18-A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte. Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity bits are output in the most significant bit of each byte. To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST is LOW. This sets the AFA, AFB, MBF1, and MBF2 flags HIGH and the EFA, EFB, AEA, AEB, FFA, and FFB flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select Almost-Full and Almost-Empty flag offset. A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-toHIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH. A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-toHIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.
ODD/ EVEN PEFA
Odd/Even Parity Select Port A Parity Error Flag
I
O (Port A)
PEFB
Port B Parity Error Flag
O (Port B)
PGA
Port A Parity Generation Port B Parity Generation Reset
I
PGB
I
RST
I
W/RA
Port A Write/Read Select Port B Write/Read Select
I
W/RB
I
5
Others parts begin by 72
72-1 72-2 72-3
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