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Part: 72V3613
Category:
Memory
-> FIFO
Description: 64 X 36 Syncfifo, 3.3V
Company: Integrated Device Technology, Inc.
Datasheet: Download 72V3613 datasheet File size : 843 kB
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Datasheet text preview:
3.3 VOLT CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 FEATURES:
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IDT72V3613
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64 x 36 storage capacity FIFO buffering data from Port A to Port B Supports clock frequencies up to 83MHz Fast access times of 8ns Free-running CLKA and CLKB may be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) Mailbox bypass registers in each direction Dynamic Port B bus sizing of 36 bits (long word), 18 bits (word), and 9 bits (byte) Selection of Big- or Little-Endian format for word and byte bus sizes Three modes of byte-order swapping on Port B Programmable Almost-Full and Almost-Empty flags Microprocessor interface control logic FF , AF flags synchronized by CLKA EF , AE flags synchronized by CLKB Passive parity checking on each Port
Parity Generation can be selected for each Port Available in 132-pin plastic quad flat package (PQF), or space saving 120-pin thin quad flat package (TQFP) Pin and functionally compatible version of the 5V operating IDT723613 Industrial temperature range (40°C to +85°C) is available ° °
DESCRIPTION:
The IDT72V3613 is a pin and functionally compatible version of the IDT723613, designed to run off a 3.3V supply for exceptionally low-power consumption. This device is a monolithic, high-speed, low-power, CMOS synchronous (clocked) FIFO memory which supports clock frequencies up to 83 MHz and has read-access times as fast as 8 ns. The 64 x 36 dual-port SRAM FIFO buffers data from port A to port B. The FIFO operates in IDT Standard mode and has flags to indicate empty and full conditions, and two programmable flags, Almost-Full (AF) and Almost-Empty (AE), to indicate when a selected number of words is stored in memory. FIFO data on port B can be output in 36bit, 18-bit, and 9-bit formats with a choice of Big- or Little-Endian configurations.
FUNCTIONAL BLOCK DIAGRAM
CLKA CSA W/RA ENA MBA
Port-A Control Logic Parity Gen/Check MBF1 PEFB PGB
Bus-MaOhitpuand tc ung t Byte Swapping Register
RST ODD/ EVEN
Mail 1 Register
Parity Generation
Input Register
RAM ARRAY
64 x 36
Output Register
Device Control
36
64 x 36
36
Write Pointer FF AF
FIFO
Read Pointer
B0 - B35
Status Flag Logic
FS0 FS1 A0 - A35 PGA PEFA MBF2
Programmable Flag Offset Registers
Port-B Por ro Cont-Bl Contirol Log c Logic
Parity Gen/Check
Mail 2 Register
EF AE CLKB CSB W/RB ENB BE SIZ0 SIZ1 SW0 SW1
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IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
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2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
MAY 2003
DSC-4661/1
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
Three modes of byte-order swapping are possible with any bus-size selection. Communication between each port can bypass the FIFO via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and may be ignored if not desired. Parity generation can be selected for data read from each port. Two or more devices may be used in parallel to create wider data paths. The IDT72V3613 is a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a continuous (free-running) port clock by
enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple interface between microprocessors and/or buses with synchronous interfaces. The Full Flag (FF) and Almost-Full (AF) flag of the FIFO are two-stage synchronized to the port clock (CLKA) that writes data into its array. The Empty Flag (EF) and Almost-Empty (AE) flag of the FIFO are two-stage synchronized to the port clock (CLKB) that reads data from its array. The IDT72V3613 is characterized for operation from 0°C to 70°C. Industrial temperature range (40°C to +85°C) is available by special order. This device is fabricated using IDT's high speed, submicron CMOS technology.
PIN CONFIGURATION
A24 A25 A26 VCC A27 A28 A29 GND A30 A31 A32 A33 A34 A35 GND B35 B34 B33 B32 B31 B30 GND B29 B28 B27 VCC B26 B25 B24 B23
A23 A22 A21 GND A20 A19 A18 A17 A16 A15 A14 A13 A12 A11 A10 GND A9 A8 A7 VCC A6 A5 A4 A3 GND A2 A1 A0 NC NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
B22 B21 GND B20 B19 B18 B17 B16 B15 B14 B13 B12 B11 B10 GND B9 B8 B7 VCC B6 B5 B4 B3 GND B2 B1 B0 EF AE NC
AF FF CSA ENA CLKA W/RA VCC PGA PEFA MBF2 MBA FS1 FS0 ODD/EVEN RST GND BE SW1 SW0 SIZ1 SIZ0 MBF1 PEFB PGB VCC W/RB CLKB ENB CSB NC
NOTE: 1 . NC = No internal connection
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
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TQFP (PN120-1, order code: PF) TOP VIEW 2
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGE
PIN CONFIGURATION (CONTINUED)
AF FF CSA ENA CLKA W/RA VCC PGA PEFA GND MBF2 MBA FS1 FS0 ODD/EVEN RST GND BE SW1 SW0 SIZ1 SIZ0 MBF1 GND PEFB PGB VCC W/RB CLKB ENB CSB NC NC
GND NC NC A0 A1 A2 GND A3 A4 A5 A6 VCC A7 A8 A9 GND A10 A11 VCC A12 A13 A14 GND A15 A16 A17 A18 A19 A20 GND A21 A22 A23 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
*
VCC A24 A25 A26 GND A27 A28 A29 VCC A30 A31 A32 GND A33 A34 A35 GND B35 B34 B33 GND B32 B31 B30 VCC B29 B28 B27 GND B26 B25 B24 VCC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
GND AE EF B0 B1 B2 GND B3 B4 B5 B6 VCC B7 B8 B9 GND B10 B11 VCC B12 B13 B14 GND B15 B16 B17 B18 B19 B20 GND B21 B22 B23
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* Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
NOTES: 1 . NC = No internal connection. 2 . Uses Yamaichi socket IC51-1324-828.
PQFP(2) (PQ132-1, order code: PQF) TOP VIEW
3
IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol A0-A35 AE AF B0-B35 BE CLKA CLKB Name Port A Data Almost-Empty Flag Almost-Full Flag Port B Data Big-Endian Select Port A Clock Port B Clock I/O I/O 36-bit bidirectional data port for side A. Description
O Programmable Almost-Empty flag synchronized to CLKB. It is LOW when Port B the number of 36-bit Port B words in the FIFO is less than or equal to the value in the offset register, X. O Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of 36-bit empty Port A empty locations in the FIFO is less than or equal to the value in the offset register, X. I/O I I I 36-bit bidirectional data port for side B Selects the bytes on port B used during byte or word FIFO reads. A LOW on BE selects the most significant bytes on B0-B35 for use, and a HIGH selects the least significant bytes. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. FF and AF are synchronized to the LOW-to-HIGH transition of CLKA. CLKB is a continuous clock that synchronizes all data transfers through port B and can be asynchronous or coincident to CLKA. Port-B byte swapping and data port sizing operations are also synchronous to the LOW-to-HIGH transition of CLKB. EF and AE are synchronized to the LOW-to-HIGH transition of CLKB. CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. The A0A35 outputs are in the high-impedance state when CSA is HIGH. CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The B0B35 outputs are in the high-impedance state when CSB is HIGH.
CSA CSB EF
Port A Chip Select Port B Chip Select Empty Flag
I I
O EF is synchronized to the LOW-to-HIGH transition of CLKB. When EF is LOW, the FIFO is empty, and Port B reads from its memory are disabled. Data can be read from the FIFO to its output register when EF is HIGH. EF is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKB after data is loaded into empty FIFO memory. I I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
ENA ENB FF
Port A Enable Port B Enable Full Flag
O FF is synchronized to the LOW-to-HIGH transition of CLKA. When FF is LOW, the FIFO is full, and Port A writes to its memory are disabled. FF is forced LOW when the device is reset and is set HIGH by the second LOW-to-HIGH transition of CLKA after reset. I I O The LOW-to-HIGH transition of RST latches the values of FS0 and FS1, which loads one of four preset values into the Almost-Full flag and Almost-Empty flag offsets. A high level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35 outputs are active, mail2 register data is output. MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is set LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port B read is selected and both SIZ1 and SIZ0 are HIGH. MBF1 is set HIGH when the device is reset. MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is set LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is set HIGH when the device is reset. Odd parity is checked on each port when ODD/EVEN is HIGH, and even parity is checked when ODD/EVEN is LOW. ODD/EVEN also selects the type of parity generated for each port if parity generation is enabled for a read operation. When any valid byte applied to terminals A0-A35 fails parity, PEFA is LOW. Bytes (Port A) are organized as A0-A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte serving as the parity bit. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the A0-A35 inputs are shared by the mail2 register to generate parity if parity generation is selected by PGA. Therefore, if a mail2 read with parity generation is set up by having CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH and PGA HIGH, the PEFA flag is forced HIGH regardless of the state of the A0-A35 inputs.
FS1, FS0 Flag Offset Selects MBA MBF1 Port A Mailbox Select Mail1 Register Flag
MBF2
Mail2 Register Flag
O
ODD/ EVEN PEFA
Odd/Even Parity Select Port A Parity Error Flag
I
O
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IDT72V3613 3.3V, CMOS CLOCKED FIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTION (CONTINUED)
Symbol PEFB Name Port B Parity Error Flag I/O Description O When any valid byte applied to terminals B0-B35 fails parity, PEFB is LOW. Bytes are organized as (Port B) B0-B8, B9-B17, B-18-B26, and B27-B35, with the most significant bit of each byte serving as the parity bit. A byte is valid when it is used by the bus size selected for port B. The type of parity checked is determined by the state of the ODD/EVEN input. The parity trees used to check the B0-B35 inputs are shared by the mail1 register to generate parity if parity generation is selected by PGB. Therefore, if a mail1 read with parity generation is set up by having CSB LOW, ENB HIGH, W/RB LOW, SIZ1 and SIZ0 HIGH and PGB HIGH, the PEFB flag is forced HIGH regardless of the state of the B0-B35 inputs. PGA Port A Parity Generation Port B Parity Generation Reset I Parity is generated for data reads from the mail2 register when PGA is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized at A0-A8, A9-A17, A18A26, and A27-A35. The generated parity bits are output in the most significant bit of each byte. Parity is generated for data reads from port B when PGB is HIGH. The type of parity generated is selected by the state of the ODD/EVEN input. Bytes are organized as B0-B8, B9-B17, B18-B26, and B27-B35. The generated parity bits are output in the most significant bit of each byte. To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST is LOW. This sets the AF, MBF1, and MBF2 flags HIGH and the EF, AE, and FF flags LOW. The LOW-to-HIGH transition of RST latches the status of the FS1 and FS0 inputs to select Almost-Full flag and Almost-Empty flag offset.
PGB
I
RST
I
SIZ0, SIZ1
Port B Bus Size Selects
I A LOW-to-HIGH transition of CLKB latches the states of SIZ0, SIZ1, and BE, and the following LOW-to(Port B) HIGH transition of CLKB implements the latched states as a port B bus size. Port B bus sizes can be long word, word, or byte. A HIGH on both SIZ0 and SIZ1 chooses a mailbox register for a port B 36-bit write or read. I At the beginning of each long word FIFO read, one of four modes of byte-order swapping is selected by (Port B) SW0 and SW1. The four modes are no swap, byte swap, word swap, and byte-word swap. Byte-order swapping is possible with any bus-size selection. I I A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH. A HIGH selects a write operation and a LOW selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is HIGH.
SW0, SW1 W/RA W/RB
Port B Byte Swap Selects Port A Write/Read Select Port B Write/Read Select
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