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Part: 72V3641
Category:
Memory
-> FIFO
Description: 1K X 36 Syncfifo, 3.3V
Company: Integrated Device Technology, Inc.
Datasheet: Download 72V3641 datasheet File size : 843 kB
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Datasheet text preview:
3.3 VOLT CMOS SyncFIFOTM 512 x 36, 1,024 x 36, and 2,048 x 36
FEATURES:
PRELIMINARY IDT72V3631 IDT72V3641 IDT72V3651
IDT72V3631 - 512 x 36 IDT72V3641 - 1,024 x 36 IDT72V3651 - 2,048 x 36 Supports clock frequencies up to 67 MHz Fast access times of 10ns Free-running CLKA and CLKB can be asynchronous or coincident (permits simultaneous reading and writing of data on a single clock edge) Clocked FIFO buffering data from Port A to Port B Synchronous read retransmit capability Mailbox register in each direction Programmable Almost-Full and Almost-Empty flags Microprocessor interface control logic Input Ready (IR) and Almost-Full (AF) flags synchronized by CLKA Output Ready (OR) and Almost-Empty (AE) flags synchronized by CLKB
Storage capacity:
Available in 132-pin plastic quad flat package (PQFP) or spacesaving 120-pin thin quad flat package (TQFP) Pin and functionally compatible versions of the 5V operating IDT723631/723641/723651 Easily expandable in width and depth Industrial temperature range (40°C to +85°C) is available
DESCRIPTION:
The IDT72V3631/72V3641/72V3651 are pin and functionally compatible versons of the IDT723631/723641/723651, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are monolithic high-speed, low-power, CMOS clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10ns. The 512/1,024/2,048 x 36 dual-port SRAM FIFO buffers data from port A to Port B. The FIFO memory has retransmit capability, which allows previously read data to be accessed again. The FIFO operates in First Word Fall Through mode and has flags to indicate empty and full conditions and conditions and two programmable flags (Almost-Full and Almost-Empty) to
FUNCTIONAL BLOCK DIAGRAM
MBF1 Mail 1 Register
Input Register
RAM ARRAY
512 x 36 1,024 x 36 2,048 x 36
Sync Retransmit Logic
RST
Reset Logic
Output Register
CLKA CSA W/RA ENA MBA
Port-A Control Logic
RTM RFM B0 - B35 OR AE
36
A0 - A35 IR AF
Write Pointer
Read Pointer
Status Flag Logic
FS0/SD FS1/SEN
10
Flag Offset Registers Port-B Control Logic CLKB CSB W/RB ENB MBB
4658 drw 01
Mail 2 Register
MBF2
AUGUST 2000
1
© 2000 Integrated Device Technology, Inc. DSC-4658/-
IDT72V3631/72V3641/72V3651 3.3V CMOS SYNCFIFOTM 512 x 36, 1,024 x 36 AND 2,048 x 36
Commercial Temperature
provide a simple interface between microprocessors and/or buses with synchronous control. The Input Ready (IR) flag and Almost-Full (AF) flag of the FIFO are twostage synchronized to CLKA. The Output Ready (OR) flag and Almost-Empty (AE) flag of the FIFO are two-stage synchronized to CLKB. Offset values for the Almost-Full and Almost-Empty flags of the FIFO can be programmed from port A or through a serial input. The IDT72V3631/72V3641/72V3651 are characterized for operation from 0oC to 70oC. Industrial temperature range (-40oC to +85oC) is available by special order. These devices are fabricated using IDT's high speed, submicron CMOS technology.
DESCRIPTION (Continued)
indicate when a selected number of words is stored in memory. Communication between each port may take place with two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Two or more devices may be used in parallel to create wider data paths. Expansion is also possible in word depth. These devices are a clocked FIFO, which means each port employs a synchronous interface. All data transfers through a port are gated to the LOWto-HIGH transition of a continuous (free-running) port clock by enable signals. The continuous clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to
PIN CONFIGURATION
NC NC VCC CLKB ENB W/RB CSB GND MBF1 GND MBB NC VCC RFM RTM FS1/SEN FS0/SD GND RST MBA MBF2 VCC AE AF VCC OR IR CSA W/RA ENA CLKA GND NC
NC B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND NC NC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
*
NC B11 B10 B9 B8 B7 VCC B6 GND B5 B4 B3 B2 B1 B0 GND A0 A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND NC NC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
NC NC A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 NC
*
4658 drw 02
Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner. PQFP (PQ132-1, order code: PQF) TOP VIEW
NOTES: 1. NC No internal connection 2. Uses Yamaichi socket IC51-1324-828
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IDT72V3631/72V3641/72V3651 3.3V CMOS SYNCFIFOTM 512 x 36, 1,024 x 36 AND 2,048 x 36
Commercial Temperature
PIN CONFIGURATION (Continued)
GND CLKA ENA W/RA CSA IR OR VCC AF AE VCC MBF2 MBA RST GND FS0/SD FS1/SEN RTM RFM VCC NC MBB GND MBF1 GND CSB W/RB ENB CLKB VCC
A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 GND A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND
GND A11 A10 A9 A8 A7 A6 GND A5 A4 A3 VCC A2 A1 A0 GND B0 B1 B2 B3 B4 B5 GND B6 VCC B7 B8 B9 B10 B11
4658 drw 03
NOTE: 1. NC No internal connection
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
TQFP (PN120-1, order code: PF) TOP VIEW 3
IDT72V3631/72V3641/72V3651 3.3V CMOS SYNCFIFOTM 512 x 36, 1,024 x 36 AND 2,048 x 36
Commercial Temperature
PIN DESCRIPTION
Symbol Name A0-A35 Port-A Data AE Almost-Empty Flag AF Almost-Full Flag B0-B35 Port-B Data CLKA Port-A Clock CLKB CSA CSB ENA ENB FS1/ SEN, Port-B Clock Port-A Chip Select Port-B Chip Select Port-A Enable Port-B Enable Flag-Offset Select 1/ Serial Enable Flag Offset 0/ Serial Data
I/O Description I/O 36-bit bidirectional data port for side A. O Programmable flag synchronized to CLKB. It is LOW when the number of words in the FIFO is less than or equal to the value in the Almost-Empty register (X). O Programmable flag synchronized to CLKA. It is LOW when the number of empty locations in the FIFO is less than or equal to the value in the Almost-Full Offset register (Y). I/O 36-bit bidirectional data port for side B. I CLKA is a continuous clock that synchronizes all data transfers through port-A and may be asynchronous or coincident to CLKB. IR and AF are synchronous to the LOW-to-HIGH transition of CLKA. I CLKB is a continuous clock that synchronizes all data transfers through port-B and may be asynchronous or coincident to CLKA. OR and AE are synchronous to the LOW-to-HIGH transition of CLKB. I CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. I CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH. I ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port-A. I ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port-B. I FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During a device reset, FS1/SEN and FS0/SD selects the flag offset programming method. Three Offset register programming methods are available: automatically load one of two preset values, parallel load from port A, and serial load. When serial load is selected for flag Offset register programming, FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on FS0/ SD into the X and Y registers. The number of bit writes required to program the Offset registers is 18/20/22 for the IDT72V3631/72V3641/72V3651 respectively. The first bit write stores the Y-register MSB and the last bit write stores the X-register LSB. IR is synchronized to the LOW-to-HIGH transition of CLKA. When IR is LOW, the FIFO is full and writes to its array are disabled. When the FIFO is in retransmit mode, IR indicates when the memory has been filled to the point of the retransmit data and prevents further writes. IR is set LOW during reset and is set HIGH after reset. A HIGH level chooses a mailbox register for a port-A read or write operation. A HIGH level chooses a mailbox register for a port-B read or write operation. When the B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO data for output. MBF1 is set LOW by the LOW-to-HIGH transition of CLKA that writes data to the mail1 register. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B read is selected and MBB is HIGH. MBF1 is set HIGH by a reset. MBF2 is set LOW by the LOW-to-HIGH transition of CLKB that writes data to the mail2 register. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port-A read is selected and MBA is HIGH. MBF2 is set HIGH by a reset. OR is synchronized to the LOW-to-HIGH transition of CLKB. When OR is LOW, the FIFO is empty and reads are disabled. Ready data is present in the output register of the FIFO when OR is HIGH. OR is forced LOW during the reset and goes HIGH on the third LOW-to-HIGH transition of CLKB after a word is loaded to empty memory. When the FIFO is in retransmit mode, a HIGH on RFM enables a LOW-to-HIGH transition of CLKB to reset the read pointer to the beginning retransmit location and output the first selected retransmit data. To reset the device, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST is LOW. The LOW-to-HIGH transition of RST latches the status of FS0 and FS1 for AF and AE offset selection. When RTM is HIGH and valid data is present in the FIFO output register (OR is HIGH), a LOW-to-HIGH transition of CLKB selects the data for the beginning of a retransmit and puts the FIFO in retransmit mode. The selected word remains the initial retransmit point until a LOW- to-HIGH transition of CLKB occurs while RTM is LOW, taking the FIFO out of retransmit mode. A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the high-impedance state when W/RA is HIGH. A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the high-impedance state when W/RB is LOW.
FS0/SD
IR MBA MBB MBF1 MBF2 OR RFM RST RTM
Input Ready Flag Port-A Mailbox Select Port-B Mailbox Select Mail1 Register Flag Mail2 Register Flag Output Ready Flag Read From Mark Reset Retransmit Mode
O I I O
O O I I I
W/RA W/RB
Port-A Write/ Read Select Port-B Write/ Read Select
I I
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IDT72V3631/72V3641/72V3651 3.3V CMOS SYNCFIFOTM 512 x 36, 1,024 x 36 AND 2,048 x 36
Commercial Temperature
ABSOLUTE MAXIMUM RATINGS OVER OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)(2)
Symbol VCC VI
(2) (2)
Rating Supply Voltage Range Input Voltage Range Output Voltage Range Input Clamp Current, (VI VCC) Output Clamp Current, (VO = VCC) Continuous Output Current, (VO = 0 to VCC) Continuous Current Through VCC or GND Storage Temperature Range
Commercial 0.5 to +4.6 0.5 to VCC+0.5 ±20 ±50 ±50 ±400 65 to 150
(3)
Unit V V V mA mA mA mA °C
VO IIK
0.5 to VCC+0.5
I OK IOUT ICC TSTG
NOTES: 1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "Recommended Operating Conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 . The input and output voltage ratings may be exceeded provided the input and output current ratings are observed. 3 . Control Inputs: maximum VI = 5.0V.
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VIH VIL IOH IO L TA Parameter Supply Voltage HIGH Level Input Voltage LOW-Level Input Voltage HIGH-Level Output Current LOW-Level Output Current Operating Free-air Temperature Min. 3.0 2 -- -- -- 0 Typ. 3.3 -- -- -- -- -- Max. 3.6 VCC+0.5 0.8 4 8 70 Unit V V V mA mA
°C
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING FREE-AIR TEMPERATURE RANGE (Unless otherwise noted)
IDT72V3631 IDT72V3641 IDT72V3651 Commercial tCLK = 15, 20 ns Min. Typ.(1) Max. 2.4 -- -- -- -- 0.5 -- -- ±5 -- -- ±5 -- -- 400 -- 4 -- -- 8 --
Symbol VOH VOL ILI IL O ICC2(2) CIN COUT
Parameter Output Logic "1" Voltage Output Logic "0" Voltage Input Leakage Current (Any Input) Output Leakage Current Standby Current Input Capacitance Output Capacitance
VCC = 3.0V, VCC = 3.0V, VCC = 3.6V, VCC = 3.6V, VCC = 3.6V, VI = 0, VO = 0,
Test Conditions IOH = 4 mA IOL = 8 mA VI = VCC or 0 VO = VCC or 0 VI = VCC 0.2V or 0 f = 1 MHz f = 1 MHZ
Unit V V µA µA µA pF pF
NOTES: 1 . All typical values are at VCC = 3.3V, TA = 25°C. 2. For additional ICC information, see Figure 1, Typical Characteristics: Supply Current (ICC) vs. Clock Frequency (fS).
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