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Part: 72V3646
Category:
Memory
-> FIFO
Description: 1K X 36 X 2 Triple-bus Fifo, 3.3V
Company: Integrated Device Technology, Inc.
Datasheet: Download 72V3646 datasheet File size : 843 kB
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3.3 VOLT CMOS TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
.EATURES:
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IDT72V3626 IDT72V3636 IDT72V3646
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Memory storage capacity: IDT72V3626256 x 36 x 2 IDT72V3636512 x 36 x 2 IDT72V36461,024 x 36 x 2 Clock frequencies up to 100 MHz (6.5ns access time) Two independent FIFOs buffer data between one bidirectional 36-bit port and two unidirectional 18-bit ports (Port C receives and Port B transmits) 18-bit (word) and 9-bit (byte) bus sizing of 18 bits (word) on Ports B and C Select IDT Standard timing (using EFA, EFB, FFA, and FFC flag functions) or First Word Fall Through Timing (using ORA, ORB, IRA, and IRC flag functions) Programmable Almost-Empty and Almost-Full flags; each has
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three default offsets (8, 16 and 64) Serial or parallel programming of partial flags Big- or Little-Endian format for word and byte bus sizes Master Reset clears data and configures FIFO, Partial Reset clears data but retains configuration settings Mailbox bypass registers for each FIFO Free-running CLKA, CLKB and CLKC may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Auto power down minimizes power dissipation Available in a space-saving 128-pin Thin Quad Flatpack (TQFP) Pin and functionally compatible versions of 5V operating IDT723626/723636/723646 Industrial temperature range (40°C to +85°C) is available ° °
.UNCTIONAL BLOCK DIAGRAM
MBF1 Mail 1 Register
Output BusMatching
Input Register
36
RAM ARRAY
256 x 36 512 x 36 1,024 x 36
36
Output Register
CLKA CSA W/RA ENA MBA MRS1 PRS1
Port-A Control Logic
18
B0-B17
FIFO1, Mail1 Reset Logic
36
Port-B Control Logic Write Pointer Read Pointer
CLKB RENB CSB MBB SIZEB
FFA/IRA AFA SPM FS0/SD FS1/SEN A0-A35 EFA/ORA AEA
FIFO1
Status Flag Logic Common Port Control Logic (B and C)
EFB/ORB AEB
Programmable Flag Offset Registers
10 FIFO2
Timing Mode
BE
Status Flag Logic Read Pointer Write Pointer FIFO2, Mail2 Reset Logic
FWFT FFC/IRC AFC MRS2 PRS2
36
Input Register
36
RAM ARRAY
Input BusMatching
Output Register
256 x 36 512 x 36 1,024 x 36 Mail 2 Register
36
18
C0-C17 CLKC WENC MBC SIZEC
4665 drw01
Port-C Control Logic
MBF2
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncFIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
AUGUST 2001
DSC-4665/4
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2001 Integrated Device Technology, Inc. All right reserved. Product specifications subject to change without notice.
IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION:
The IDT72V3626/72V3636/72V3646 are pin and functionally compatible versions of the IDT723626/723636/723646, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are a monolithic, high-speed, low-power, CMOS Triple Bus synchronous (clocked) FIFO memory which supports clock frequencies up to 100 MHz and has read access times as fast as 6.5ns. Two independent 256/512/1,024 x 36 dual-port SRAM
FIFOs on board each chip buffer data between a bidirectional 36-bit bus (Port A) and two unidirectional 18-bit buses (Port B transmits data, Port C receives data.) FIFO data can be read out of Port B and written into Port C using either 18-bit or 9-bit formats with a choice of Big- or Little-Endian configurations. These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
PIN CON.IGURATION
CSA FFA/IRA EFA/ORA PRS1 VCC AFA AEA MBF2 MBA MRS1 FS0/SD CLKC GND FS1/SEN MRS2 MBB MBF1 VCC AEB AFC EFB/ORB FFC/IRC GND CSB WENC RENB
INDEX
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
W/RA ENA CLKA GND A35 A34 A33 A32 Vcc A31 A30 GND A29 A28 A27 A26 A25 A24 A23 BE/FWFT GND A22 Vcc A21 A20 A19 A18 GND A17 A16 A15 A14 A13 Vcc A12 GND A11 A10
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
CLKB PRS2 VCC C17 C16 C15 C14 GND MBC C13 C12 C11 C10 C9 C8 VCC C7 C6 SIZEB GND C5 C4 C3 C2 C1 C0 GND B17 B16 SIZEC VCC B15 B14 B13 B12 GND B11 B10
A9 A8 A7 A6 GND A5 A4 A3 SPM VCC A2 A1 A0 GND B0 B1 B2 B3 B4 B5 GND B6 VCC B7 B8 B9
4665 drw 02
TQFP (PK128-1, order code: PF) TOP VIEW 2
IDT72V3626//72V336/6/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFOTM IDT72V3 626 72V3663 72V3646 CMOS 3.3V Triple Bus SyncFIFOTM WIiTh Bus-Matching 256x36x2, 512x36x2, 1,024x36x21,024 x 36 x 2 w t H BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2,
COMMERCIAL TEMPERATURE RANGE
each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control. Communication between each port may bypass the FIFOs via two mailbox registers. The mailbox registers' width matches the selected bus width of ports B and C. Each mailbox register has a flag (MBF1 and MBF2) to signal when new mail has been stored. Two kinds of reset are available on these FIFOs: Master Reset and Partial Reset. Master Reset initializes the read and write pointers to the first location of the memory array and selects serial flag programming, parallel flag programming, or one of three possible default flag offset settings, 8, 16 or 64. Each FIFO has its own, independent Master Reset pin, MRS1 and MRS2. Partial Reset also sets the read and write pointers to the first location of the memory. Unlike Master Reset, any settings existing prior to Partial Reset (i.e., programming method and partial flag default offsets) are retained. Partial Reset is useful since it permits flushing of the FIFO memory without changing any configuration settings. Each FIFO has its own, independent Partial Reset pin, PRS1 and PRS2. These devices have two modes of operation: In the IDT Standard mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First Word Fall Through mode (FWFT), the first word written to an empty FIFO appears automatically on the outputs, no read operation required (Nevertheless, accessing subsequent words does necessitate a formal read request). The state of the BE/FWFT pin during Master Reset determines the mode in use. Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFC/IRC). The EF and FF functions are selected in the IDT Standard mode. EF indicates whether or not the FIFO memory is empty. FF shows whether the memory is
full or not. The IR and OR functions are selected in the First Word Fall Through mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a programmable Almost-Full flag (AFA and AFC). AEA and AEB indicate when a selected number of words remain in the FIFO memory. AFA and AFC indicate when the FIFO contains more than a selected number of words. FFA/IRA, FFC/IRC, AFA and AFC are two-stage synchronized to the Port Clock that writes data into its array. EFA/ORA, EFB/ORB, AEA, and AEB are two-stage synchronized to the Port Clock that reads data from its array. Programmable offsets for AEA, AEB, AFA, AFC are loaded in parallel using Port A or in serial via the SD input. The Serial Programming Mode pin (SPM) makes this selection. Three default offset settings are also provided. The AEA and AEB threshold can be set at 8, 16 or 64 locations from the empty boundary and the AFA and AFC threshold can be set at 8, 16 or 64 locations from the full boundary. All these choices are made using the FS0 and FS1 inputs during Master Reset. Two or more FIFOs may be used in parallel to create wider data paths. Such a width expansion requires no additional, external components. Furthermore, two IDT72V3626/72V3636/72V3646 FIFOs can be combined with unidirectional FIFOs capable of First Word Fall Through timing (i.e. the SuperSync FIFO family) to form a depth expansion. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption (ICC) is at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT72V3626/72V3636/72V3646 are characterized for operation from 0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by special order. They are fabricated using IDT's high speed, submicron CMOS technology.
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IDT72V3626/72V3636/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFOTM WITH BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol A0-A35 AEA AEB AFA AFC B0-B17 BE/FWFT Name Port A Data Port A AlmostEmpty Flag Port B AlmostEmpty Flag Port A AlmostFull Flag Port C AlmostFull Flag Port B Data Big-Endian/ First Word Fall Through Select I/O I/O O O O O O I 36-bit bidirectional data port for side A. Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2. Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1. Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1. Programmable Almost-Full flag synchronized to CLKC. It is LOW when the number of empty locations in FIFO2 is less than or equal to the value in the Almost-Full C Offset register, Y2. 18-bit output data port for side B. This is a dual purpose pin. During Master Reset, a HIGH on BE will select Big-Endian operation. In this case, depending on the bus size, the most significant byte or word on Port A is read from Port B first (A-to-B data flow) or is written to Port C first (C-to-A data flow). A LOW on BE will select Little-Endian operation. In this case, the least significant byte or word on Port A is read from Port B first (A-to-B data flow) or is written to Port C first (C-to-A data flow). After Master Reset, this pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must be static throughout device operation. C0-C17 CLKA Port C Data Port A Clock I I 18-bit input data port for side C. CLKA is a continuous clock that synchronizes all data transfers through Port A and can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH transition of CLKA. CLKB is a continuous clock that synchronizes all data transfers through Port B and can be asynchronous or coincident to CLKA. EFB/ORB and AEB are synchronized to the LOW-to-HIGH transition of CLKB. CLKC is a continuous clock that synchronizes all data transfers through Port C and can be asynchronous or coincident to CLKA. FFC/IRC and AFC are synchronized to the LOW-to-HIGH transition of CLKC. CSA must be LOW to enable to LOW-to-HIGH transition of CLKA to read or write on Port A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read data on Port B. The B0-B17 outputs are in the high-impedance state when CSB is HIGH. This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the presence of valid data on the A0-A35 outputs, available for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA. This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the presence of valid data on the B0-B17 outputs, available for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB. ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on Port A. This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA. This is a dual function pin. In the IDT Standard mode, the FFC function is selected. FFC indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRC function is selected. IRC indicates whether or not there is space available for writing to the FIFO2 memory. FFC/IRC is synchronized to the LOW-to-HIGH transition of CLKC. Description
CLKB CLKC CSA CSB EFA/ORA
Port B Clock Port C Clock Port A Chip Select Port B Chip Select Port A Empty/ Output Ready Flag Port B Empty/ Output Ready Flag
I I I I O
EFB/ORB
O
ENA FFA/IRA
Port A Enable Port A Full/ Input Ready Flag
I O
FFC/IRC
Port C Full/ Input Ready Flag
O
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IDT72V3626//72V336/6/72V3646 CMOS 3.3V TRIPLE BUS SyncFIFOTM IDT72V3 626 72V3663 72V3646 CMOS 3.3V Triple Bus SyncFIFOTM WIiTh Bus-Matching 256x36x2, 512x36x2, 1,024x36x21,024 x 36 x 2 w t H BUS-MATCHING 256 x 36 x 2, 512 x 36 x 2,
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (Continued)
Symbol Name I/O Description FS1/SEN Flag Offset Select 1/ I FS1/SEN and FS0/SD are dual-purpose inputs used for flag Offset register programming. During Master Reset, Serial Enable, FS1/SEN and FS0/SD, together with SPM, select the flag offset programming method. Three Offset register programming methods are available: automatically load one of three preset values (8, 16, or 64), parallel FS0/SD Flag Offset Select 0/ load from Port A, and serial load. Serial Data When serial load is selected for flag Offset register programming, FS1/SEN is used as an enable synchronous to the LOW-to-HIGH transition of CLKA. When FS1/SEN is LOW, a rising edge on CLKA load the bit present on FS0/SD into the X and Y registers. The number of bit writes required to program the Offset registers is 32 for the 72V3626, 36 for the 72V3636, and 40 for the 72V3646. The first bit write stores the Y-register (Y1) MSB and the last bit write stores the X-register (X2) LSB. MBA Port A Mailbox I A HIGH level on MBA chooses a mailbox register for a Port A read or write operation. When the A0-A35 Select outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects FIFO2 output-register data for output. MBB Port B Mailbox Select Port C Mailbox Select Mail1 Register Flag Mail2 Register Flag Master Reset I A HIGH level on MBB chooses a mailbox register for a Port B read operation. When the B0-B17 outputs are active, a HIGH level on MBB selects data from the mail1 register for output and a LOW level selects FIFO1 output register data for output. A HIGH level on MBC chooses the mail2 register for a Port C write operation. This pin must be HIGH during Master Reset.
MBC MBF1
I
MBF2
O MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a Port B read is selected and MBB is HIGH. MBF1 is set HIGH following either a Master or Partial Reset of FIFO1. O MBF2 is set LOW by a LOW-to-HIGH transition of CLKC that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a Port A read is selected and MBA is HIGH. MBF2 is set HIGH following either a Master or Partial Reset of FIFO2. I A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets the Port B output register to all zeroes. A LOW-to-HIGH transition on MRS1 selects the programming method (serial or parallel) and one of three programmable flag default offsets for FIFO1 and FIFO2. It also configures ports B and C for bus size and endian arrangement. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while MRS1 is LOW. I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets the Port A output register to all zeroes. A LOW-to-HIGH transition on MRS2, toggled simultaneously with MRS1, selects the programming method (serial or parallel) and one of the three flag default offsets for FIFO2. Four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKC must occur while MRS2 is LOW.
MRS1
MRS2
Master Reset
PRS1
Partial Reset
I
PRS2
Partial Reset
A LOW on this pin initializes the FIFO1 read and write pointers to the first location of memory and sets thePort B output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are all retained. I A LOW on this pin initializes the FIFO2 read and write pointers to the first location of memory and sets thePort A output register to all zeroes. During Partial Reset, the currently selected bus size, endian arrangement, programming method (serial or parallel), and programmable flag settings are all retained. RENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read data on Port B. SIZEB determines the bus width of Port B. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin selects word (18-bit) bus size. SIZEB works with SIZEC and BE to select the bus size and endian arrangement for ports B and C. The level of SIZEB must be static throughout device operation.
RENB SIZEB
Port B Read Enable Port B Bus Size Select Port C Bus Size Select Serial Programming Mode Port C Write Enable Port A Write/ Read Select
I I
SIZEC
I
SPM WENC W/RA
SIZEC determines the bus width of Port C. A HIGH on this pin selects byte (9-bit) bus size. A LOW on this pin selects word (18-bit) bus size. SIZEC works with SIZEB and BE to select the bus size and endian arrangement for ports B and C. The level of SIZEC must be static throughout device operation. I A LOW on this pin selects serial programming of partial flag offsets. A HIGH on this pin selects parallel programming or default offsets (8, 16, or 64). WENC must be HIGH to enable a LOW-to-HIGH transition of CLKC to write data on Port C. A HIGH selects a write operation and a LOW selects a read operation on Port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH.
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72-1 72-2 72-3
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