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Part: 72V3672
Category:
Memory
-> FIFO
Description: 8K X 36 X 2 Syncbififo, 3.3V
Company: Integrated Device Technology, Inc.
Datasheet: Download 72V3672 datasheet File size : 843 kB
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Datasheet text preview:
3.3 VOLT CMOS SyncBiFIFOTM 2,048 x 36 x 2 4,096 x 36 x 2 8,192 x 36 x 2
FEATURES:
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PRELIMINARY IDT72V3652 IDT72V3662 IDT72V3672
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Memory storage capacity: IDT72V3652 2,048 x 36 x 2 IDT72V3662 4,096 x 36 x 2 IDT72V3672 8,192 x 36 x 2 Supports clock frequencies up to 100MHz Fast access times of 6.5ns Free-running CLKA and CLKB may be asynchronous or coincident (simultaneous reading and writing of data on a single clock edge is permitted) Two independent clocked FIFOs buffering data in opposite directions Mailbox bypass register for each FIFO Programmable Almost-Full and Almost-Empty flags Microprocessor Interface Control Logic FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB
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Select IDT Standard timing (using EFA, EFB, FFA and FFB flags functions) or First Word Fall Through timing (using ORA, ORB, IRA and IRB flag functions) Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving 120-pin Thin Quad Flatpack (TQFP) Pin and functionally compatible versions of the 5V operating IDT723652/723662/723672 Pin compatible to the lower density parts, IDT72V3622/72V3632/ 72V3642 Industrial temperature range (40°C to +85°C) is available ° °
DESCRIPTION:
The IDT72V3652/72V3662/72V3672 are pin and functionally compatible versions of the IDT723652/723662/723672, designed to run off a 3.3V supply for exceptionally low-power consumption. These devices are monolithic, highspeed, low-power, CMOS Bidirectional SyncFIFO (clocked) memories which support clock frequencies up to 100MHz and have read access times as fast
FUNCTIONAL BLOCK DIAGRAM
MBF1 CLKA CSA W/RA ENA MBA Mail 1 Register Input Register Output Register Port-A Control Logic RAM ARRAY 2,048 x 36 4,096 x 36 8,192 x 36
RST1
FIFO1, Mail1 Reset Logic
36
36
Write Pointer
Read Pointer EFB/ORB AEB
FFA/IRA AFA
FIFO 1
Status Flag Logic
FS0 FS1 A0 - A35
13
Programmable Flag Offset Registers
FIFO 2
Timing Mode
FWFT B0 - B35
EFA/ORA AEA
Status Flag Logic Write Pointer RAM ARRAY 2,048 x 36 4,096 x 36 8,192 x 36 Mail 2 Register
36
FFB/IRB AFB
36
Read Pointer
Output Register
FIFO2, Mail2 Reset Logic Input Register
RST2
Port-B Control Logic
CLKB CSB W/RB ENB MBB
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MBF2
The SyncBiFIFO is a trademark and the IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL TEMPERATURE RANGE
© 2001 Integrated Device Technology, Inc.
MARCH 2001
DSC-4660/2
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IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
as 6.5ns. Two independent 2,048/4,096/8,192 x 36 dual-port SRAM FIFOs on board each chip buffer data in opposite directions. Communication between each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. These devices are a synchronous (clocked) FIFO, meaning each port employs a synchronous interface. All data transfers through a port are gated to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for each port are independent of one another and can be asynchronous or coincident. The enables for each port are arranged to provide a simple bidirectional interface between microprocessors and/or buses with synchronous control.
These devices have two modes of operation: In the IDT Standard mode, the first word written to an empty FIFO is deposited into the memory array. A read operation is required to access that word (along with all other words residing in memory). In the First Word Fall Through mode (FWFT), the first long-word (36-bit wide) written to an empty FIFO appears automatically on the outputs, no read operation required (Nevertheless, accessing subsequent words does necessitate a formal read request). The state of the FWFT pin during FIFO operation determines the mode in use. Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/ IRB). The EF and FF functions are selected in the IDT Standard mode. EF indicates whether or not the FIFO memory is empty. FF shows whether the
PIN CONFIGURATION
NC NC VCC CLKB ENB W/RB CSB GND FFB/IRB EFB/ORB AFB AEB VCC MBF1 MBB RST2 FS1 GND FS0 RST1 MBA MBF2 AEA AFA VCC EFA/ORA FFA/IRA CSA W/RA ENA CLKA GND NC
NC B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND NC NC 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117
NC B11 B10 B9 B8 B7 VCC B6 GND B5 B4 B3 B2 B1 B0 GND A0 A1 A2 VCC A3 A4 A5 GND A6 A7 A8 A9 A10 A11 GND NC NC
51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83
116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84
NC NC A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 FWFT A22
VCC
A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12 NC
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*Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PQFP(2) (PQ132-1, order code: PQF) TOP VIEW
NOTES: 1. NC no internal connection 2 . Uses Yamaichi socket IC51-1324-828
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IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
memory is full or not. The IR and OR functions are selected in the First Word Fall Through mode. IR indicates whether or not the FIFO has available memory locations. OR shows whether the FIFO has data available for reading or not. It marks the presence of valid data on the outputs. Each FIFO has a programmable Almost-Empty flag (AEA and AEB) and a programmable Almost-Full flag (AFA and AFB). AEA and AEB indicate when a selected number of words remain in the FIFO memory. AFA and AFB indicate when the FIFO contains more than a selected number of words. FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the port clock that writes data into its array. EFA/ORA, EFB/ORB, AEA and AEB are two-stage synchronized to the port clock that reads data from its array. Programmable offsets for AEA, AEB, AFA and AFB are loaded by using Port A. Three default offset settings are also provided. The AEA and AEB
threshold can be set at 8, 16 or 64 locations from the empty boundary and the AFA and AFB threshold can be set at 8, 16 or 64 locations from the full boundary. All these choices are made using the FS0 and FS1 inputs during Reset. Two or more devices may be used in parallel to create wider data paths. If, at any time, the FIFO is not actively performing a function, the chip will automatically power down. During the power down state, supply current consumption (ICC) is at a minimum. Initiating any operation (by activating control inputs) will immediately take the device out of the power down state. The IDT72V3652/72V3662/72V3672 are characterized for operation from 0°C to 70°C. Industrial temperature range (-40°C to +85°C) is available by special order. They are fabricated using IDT's high speed, submicron CMOS technology.
PIN CONFIGURATION (CONTINUED)
GND CLKA ENA W/RA CSA FFA/IRA EFA/ORA VCC AFA AEA MBF2 MBA RST1 FS0 GND FS1 RST2 MBB MBF1 VCC AEB AFB EFB/ORB FFB/IRB GND CSB W/RB ENB CLKB VCC 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91
A35 A34 A33 A32 VCC A31 A30 GND A29 A28 A27 A26 A25 A24 A23 FWFT A22 VCC A21 A20 A19 A18 GND A17 A16 A15 A14 A13 VCC A12
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61
B35 B34 B33 B32 GND B31 B30 B29 B28 B27 B26 VCC B25 B24 GND B23 B22 B21 B20 B19 B18 GND B17 B16 VCC B15 B14 B13 B12 GND
GND A11 A10 A9 A8 A7 A6 GND A5 A4 A3 VCC A2 A1 A0 GND B0 B1 B2 B3 B4 B5 GND B6 VCC B7 B8 B9 B10 B11
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TQFP (PN120-1, order code: PF) TOP VIEW 3
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
Symbol A0-A35 AEA AEB AFA AFB B0 - B35 CLKA Name Port A Data Port A AlmostEmpty Flag Port B AlmostEmpty Flag Port A AlmostFull Flag Port B AlmostFull Flag Port B Data Port A Clock I/O I/0 O (Port A) O (Port B) O (Port A) O (Port B) I/O I 36-bit bidirectional data port for side A. Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2. Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1. Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1. Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty locations in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2. 36-bit bidirectional data port for side B. CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or coincident to CLKB. FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH transition of CLKA. CLKB is a continuous clock that synchronizes all data transfers through port Band can be asynchronous or coincident to CLKA. FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH transition of CLKB. CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A. The A0-A35 outputs are in the high-impedance state when CSA is HIGH. CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The B0- B35 outputs are in the high-impedance state when CSB is HIGH. This is a dual function pin. In the IDT Standard mode, the EFA function is selected. EFA indicates whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA indicates the presence of valid data on A0-A35 outputs, available for reading. EFA/ORA is synchronized to the LOW-to-HIGH transition of CLKA. This is a dual function pin. In the IDT Standard mode, the EFB function is selected. EFB indicates whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB indicates the presence of valid data on B0-B35 outputs, available for reading. EFB/ORB is synchronized to the LOW-to-HIGH transition of CLKB. ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A. ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. This is a dual function pin. In the IDT Standard mode, the FFA function is selected. FFA indicates whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA indicates whether or not there is space available for writing to the FIFO1 memory. FFA/IRA is synchronized to the LOW-to-HIGH transition of CLKA. This is a dual function pin. In the IDT Standard mode, the FFB function is selected. FFB indicates whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB indicates whether or not there is space available for writing to the FIFO2 memory. FFB/IRB is synchronized to the LOW-to-HIGH transition of CLKB. This pin selects the timing mode. A HIGH on FWFT selects IDT Standard mode, a LOW selects First Word Fall Through mode. Once the timing mode has been selected, the level on FWFT must be static throughout device operation. A LOW-to-HIGH transition of the FIFO Reset input latches the values of FS0 and FS1. If either FS0 or FS1 is HIGH when the FIFO Reset input goes HIGH, one of three preset values is selected as the offset for FIFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously and both FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1 load the AlmostEmpty and Almost-Full offsets for both FIFOs. Description
CLKB
Port B Clock
I
CSA CSB EFA/ORA
Port A Chip Select Port B Chip Select Port A Empty/ Output Ready Flag Port B Empty/ Output Ready Flag Port A Enable Port B Enable Port A Full/ Input Ready Flag Port B Full/ Input Ready Flag First Word Fall Through Mode Flag Offset Selects
I I O
EFB/ORB
O
ENA ENB FFA/IRA
I I O
FFB/IRB
O
FWFT
I
FS1, FS0
I
4
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM 2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
PIN DESCRIPTIONS (Continued)
Symbol MBA Name Port A Mailbox Select Port B Mailbox Select Mail1 Register Flag I/O I Description A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a LOW level selects FIFO2 output register data for output. A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and a LOW level selects FIFO1 output register data for output. MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is set HIGH when FIFO1 is reset. MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is also set HIGH when FIFO2 is reset. To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0 and FS1 for AFA and AEB offset selection. FIFO1 must be reset upon power up before data is written to its RAM. To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur while RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0 and FS1 for AFB and AEA offset selection. FIFO2 must be reset upon power up before data is written to its RAM. A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/RA is HIGH. A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when W/RB is LOW.
MBB
I
MBF1
O
MBF2
Mail2 Register Flag
O
RST1
FIFO1 Reset
I
RST2
FIFO2 Reset
I
W/RA W/RB
Port A Write/ Read Select Port B Write/ Read Select
I I
5
Others parts begin by 72
72-1 72-2 72-3
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